公开(公告)号：US20240223769A1

公开(公告)日：2024-07-04

申请号：US18540046

申请日：2023-12-14

Applicant: QUALCOMM Incorporated

Inventor： Zhi Zhang ,  Pavel Nikitin ,  Han Huang ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/137 ,  H04N19/105 ,  H04N19/176

CPC classification number: H04N19/137 ,  H04N19/105 ,  H04N19/176

Abstract: A method of decoding video data includes determining a vector predictor for a current block; determining a first set of vector difference candidates based on a first pel-interval, the first pel-interval defining a first distance between consecutive vector difference candidates in the first set of vector difference candidates starting with the vector predictor; determining a second set of vector difference candidates based on the first set of vector difference candidates and a second pel-interval, the second pel-interval defining a second distance between consecutive vector difference candidates in the second set of vector difference candidates; constructing a vector difference candidate list based on the second set of vector difference candidates; determining a vector for the current block based on the vector predictor and a vector difference from the vector difference candidate list; and reconstructing the current block based on the vector for the current block.

公开(公告)号：US20240179342A1

公开(公告)日：2024-05-30

申请号：US18507544

申请日：2023-11-13

Applicant: QUALCOMM Incorporated

Inventor： Yan Zhang ,  Han Huang ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/52 ,  H04N19/105 ,  H04N19/139 ,  H04N19/176 ,  H04N19/70

CPC classification number: H04N19/52 ,  H04N19/105 ,  H04N19/139 ,  H04N19/176 ,  H04N19/70

Abstract: A video coder is configured to receive a first block of video data to be coded using adaptive affine decoder side motion vector refinement (DMVR). The video coder may determine to set a first motion vector difference (MVD) for a first reference picture list to zero, and then refine control point motion vectors (CPMVs) associated with a second reference picture list to generate refined CPMVs. The video coder may then code the first block of video data using the refined CPMVs.

公开(公告)号：US20240129481A1

公开(公告)日：2024-04-18

申请号：US18471131

申请日：2023-09-20

Applicant: QUALCOMM Incorporated

Inventor： Han Huang ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/139 ,  H04N19/176

CPC classification number: H04N19/139 ,  H04N19/176

Abstract: A video coder may be configured to partition a coding block into subblocks, and generate initial subblock motion vectors for a plurality of the subblocks. The video coder may further refine the initial subblock motion vectors for the plurality of the subblocks using decoder side motion vector refinement to produce refined subblock motion vectors for the plurality of the subblocks, and perform a linear regression on the refined subblock motion vectors and coordinates of the plurality of the subblocks to derive an affine motion model. The video coder may then code the coding block using the derived affine motion model.

公开(公告)号：US20240121426A1

公开(公告)日：2024-04-11

申请号：US18467513

申请日：2023-09-14

Applicant: QUALCOMM Incorporated

Inventor： Han Huang ,  Yan Zhang ,  Zhi Zhang ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/52 ,  H04N19/105 ,  H04N19/119 ,  H04N19/127 ,  H04N19/139 ,  H04N19/159 ,  H04N19/176 ,  H04N19/56

CPC classification number: H04N19/52 ,  H04N19/105 ,  H04N19/119 ,  H04N19/127 ,  H04N19/139 ,  H04N19/159 ,  H04N19/176 ,  H04N19/56

Abstract: Encoding and decoding video data using an affine decoder side motion vector derivation (DMVR) mode includes receiving a block of video data to be decoded using the affine DMVR mode, and dividing the block into a plurality of subblocks. A video encoder and video decoder may determine a final offset for the affine DMVR mode using a first subset of the plurality of subblocks. The video encoder and decoder may code the block of video data using the final offset to generate a coded block of video data.

公开(公告)号：US11924410B2

公开(公告)日：2024-03-05

申请号：US17662140

申请日：2022-05-05

Applicant: QUALCOMM Incorporated

Inventor： Han Huang ,  Yao-Jen Chang ,  Vadim Seregin ,  Chun-Chi Chen ,  Marta Karczewicz

IPC: H04N19/105 ,  H04N19/176 ,  H04N19/51 ,  H04N19/593 ,  H04N19/70

CPC classification number: H04N19/105 ,  H04N19/176 ,  H04N19/51 ,  H04N19/593 ,  H04N19/70

Abstract: An example device for decoding video data includes one or more processors implemented in circuitry and configured to: generate an inter-prediction block for a current block of video data; generate an intra-prediction block for the current block of video data; generate a final prediction block for the current block of video data from the inter-prediction block and the intra-prediction block, including performing each of combined inter/intra prediction (CIIP) mode, overlapped block motion compensation (OBMC), and luma mapping with chroma scaling (LMCS) while generating the final prediction block; and decode the current block of video data using the final prediction block. To generate the final prediction block, the processors may perform LMCS on a first inter-prediction sub-block, combine the LMCS-mapped first inter-prediction sub-block with the intra-prediction block using CIIP, and perform OBMC between the first CIIP prediction block and a second inter-prediction sub-block.

公开(公告)号：US20240015333A1

公开(公告)日：2024-01-11

申请号：US18338886

申请日：2023-06-21

Applicant: QUALCOMM Incorporated

Inventor： Chun-Chi Chen ,  Han Huang ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/70 ,  H04N19/176

CPC classification number: H04N19/70 ,  H04N19/176

Abstract: A device for decoding video data comprises one or more processors configured to: obtain a syntax element from a bitstream that includes an encoded representation of the video data; determine, based on the syntax element, that a template-matching tool is enabled; based on the template-matching tool being enabled, applying the template-matching tool to generate a prediction block for a current coding unit (CU) of the video data; and reconstruct the current CU based on the prediction block for the current CU.

公开(公告)号：US11849131B2

公开(公告)日：2023-12-19

申请号：US16802352

申请日：2020-02-26

Applicant: QUALCOMM Incorporated

Inventor： Han Huang ,  Wei-Jung Chien ,  Marta Karczewicz

IPC: H04N7/12 ,  H04N19/44 ,  H04N19/137 ,  H04N19/176 ,  H04N19/159 ,  H04N19/119 ,  H04N19/63 ,  H04N19/189 ,  H04N19/64

CPC classification number: H04N19/44 ,  H04N19/119 ,  H04N19/137 ,  H04N19/159 ,  H04N19/176 ,  H04N19/189 ,  H04N19/63 ,  H04N19/647

Abstract: A video encoder and/or video decoder may determine the size of subblocks of a block of video data, where the block of video data is to be encoded or decoded using subblock affine motion compensation mode. The video encoder and/or video decoder may receive a block of video data to be coded using a subblock affine motion compensation mode, determine a size of one or more subblocks of the block based on one or more of an inter prediction direction or affine motion parameters of the block, partition the block into the one or more subblocks based on the determined size, and code the one or more subblocks using the subblock affine motion compensation mode.

公开(公告)号：US20230336713A1

公开(公告)日：2023-10-19

申请号：US18175988

申请日：2023-02-28

Applicant: QUALCOMM Incorporated

Inventor： Han Huang ,  Marta Karczewicz ,  Vadim Seregin

IPC: H04N19/105 ,  H04N19/70

CPC classification number: H04N19/105 ,  H04N19/70

Abstract: Example techniques and devices are disclosed for coding video data. An example device includes memory configured to store the video data and one or more processors implemented in circuitry and communicatively coupled to the memory. The one or more processors are configured to determine that multiple-hypothesis prediction (MHP) is enabled. The one or more processors are configured to, based on determining that MHP is enabled, determine a maximum number of merge candidates for a MHP merge candidate list. The one or more processors are configured to, based on the maximum number of merge candidates for the MHP merge candidate list, determine the MHP merge candidate list. The one or more processors are configured to code the video data based on the MHP merge candidate list.

公开(公告)号：US11785223B2

公开(公告)日：2023-10-10

申请号：US17321302

申请日：2021-05-14

Applicant: Qualcomm Incorporated

Inventor： Vadim Seregin ,  Wei-Jung Chien ,  Han Huang ,  Marta Karczewicz

IPC: H04N19/433 ,  H04N19/14 ,  H04N19/105 ,  H04N19/176 ,  H04N19/423 ,  H04N19/119

CPC classification number: H04N19/14 ,  H04N19/105 ,  H04N19/119 ,  H04N19/176 ,  H04N19/423

Abstract: A video coder can be configured to code video data by determining a first block size threshold for a block of video data; determining a second block size threshold, wherein the second block size threshold is smaller than the first block size threshold; partitioning the block of video data into smaller sub-blocks; in response to determining that a first partition of the partitioned block is smaller or equal to the first block size threshold, determining that blocks within the partition belong to a parallel estimation area; and in response to determining that a second partition of the partitioned block is smaller or equal to the second block size threshold, determining that blocks within the second partition belong to an area for a shared candidate list.

公开(公告)号：US20230308642A1

公开(公告)日：2023-09-28

申请号：US18325738

申请日：2023-05-30

Applicant: QUALCOMM Incorporated

Inventor： Chun-Chi Chen ,  Han Huang ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/186 ,  H04N19/51 ,  G06T9/00 ,  H04N19/189

CPC classification number: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/186 ,  H04N19/51 ,  G06T9/004 ,  H04N19/189

Abstract: An example device for decoding video data includes memory configured to store the video data and one or more processors implemented in circuitry and communicatively coupled to the memory. The one or more processors are configured to reshape a pixel domain reference template block using a forward mapping function into a mapped domain reference template block and derive local illumination compensation (LIC) model parameters from the mapped domain reference template block and a mapped domain neighboring reconstruction template block. The one or more processors are configured to apply the LIC model parameters to motion-compensated prediction signals and decode the video data based on the application of the LIC model parameters.