公开(公告)号：US20140340248A1

公开(公告)日：2014-11-20

申请号：US14052479

申请日：2013-10-11

申请人： Linear Technology Corporation

发明人： Gerd TRAMPITSCH

IPC分类号： H03M3/00

CPC分类号： H03M3/472 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1225 ,  H03M3/30 ,  H03M3/39 ,  H03M3/458 ,  H03M3/464

摘要： A method and an ADC circuit use multiple SD modulations on an analog value and apply digital post-processing of the pulse density modulation (PDM) streams from the SD modulations obtaining a higher resolution in the digital output value for a given oversampling ratio. SD ADC does not face the constraint of conversion time doubling for each additional bit of resolution. In one implementation, an SD ADC includes conversions in SD phase and a resolution-boosting phase. During SD phase, MSBs of the digital output value are generated from the sampled analog value using a first SD conversion. At the end of SD phase, the sampled analog value is reduced to “residual quantization error,” which remains in a capacitor of an integrator of SD ADC. In resolution-boosting phase, the LSBs of the digital output value are generated from residual quantization error using a second SD conversion that provides at least the LSBs.

摘要翻译： 一种方法和ADC电路在模拟值上使用多个SD调制，并对来自SD调制的脉冲密度调制（PDM）流的数字后处理在给定的过采样比获得更高分辨率的数字输出值中。 SD ADC不会面临每个额外的分辨率的转换时间加倍的约束。 在一个实现中，SD ADC包括SD阶段和分辨率提升阶段的转换。 在SD相位期间，使用第一次SD转换从采样的模拟值产生数字输出值的MSB。 在SD相结束时，采样的模拟值减少到残留在SD ADC积分器的电容器中的“残留量化误差”。 在分辨率提升阶段，使用提供至少LSB的第二SD转换，从残余量化误差产生数字输出值的LSB。

公开(公告)号：US08878710B2

公开(公告)日：2014-11-04

申请号：US13677674

申请日：2012-11-15

申请人： STMicroelectronics International N.V.

发明人： Ankur Bal ,  Neha Bhargava ,  Anupam Jain

IPC分类号： H03M3/00 ,  H03M1/12

CPC分类号： H03M3/30 ,  H03M3/344 ,  H03M3/376 ,  H03M3/462

摘要： In an embodiment, a set of input samples are filtered to provide a set of filtered samples using an N-tap filter. A steady-state-response-output sample of the N-tap filter is determined from a N/2th sample of the set of filtered samples.

摘要翻译： 在一个实施例中，对一组输入样本进行滤波，以使用N抽头滤波器提供一组滤波样本。 N抽头滤波器的稳态响应输出样本由滤波样本集合的第N / 2个样本确定。

公开(公告)号：US20140167993A1

公开(公告)日：2014-06-19

申请号：US14098579

申请日：2013-12-06

申请人： REALTEK SEMICONDUCTOR CORP.

发明人： Ming-Cheng Chiang ,  Li-Lung Kao

IPC分类号： H03M1/08

CPC分类号： H03M1/089 ,  G09G3/3648 ,  H03M1/00 ,  H03M1/0665 ,  H03M1/68 ,  H03M1/747 ,  H03M1/806 ,  H03M3/30 ,  H03M3/502

摘要： Hybrid digital-to-analog converter and method thereof are provided. The hybrid digital-to-analog converter (DAC) includes a data processor, at least one first type DAC, at least one second type DAC, and an output circuit. The data processor processes an input digital signal to output at least one of first and second digital signals which are related to a higher bit portion and a lower bit portion of the input digital signal, respectively. If the data processor outputs the first digital signal to the first type DAC, the first type DAC converts the first digital signal. The at least one second type DAC receives and converts the second digital signal outputted from the data processor. The output circuit receives at least one output signal of the first and the second type DACs to output an output analog signal.

摘要翻译： 提供了混合数模转换器及其方法。 混合数模转换器（DAC）包括数据处理器，至少一个第一类型DAC，至少一个第二类型DAC和输出电路。 数据处理器处理输入数字信号以分别输出与输入数字信号的较高位部分和较低位部分相关的第一和第二数字信号中的至少一个。 如果数据处理器将第一数字信号输出到第一类型DAC，则第一类DAC转换第一数字信号。 所述至少一个第二类型DAC接收并转换从数据处理器输出的第二数字信号。 输出电路接收第一和第二类型DAC的至少一个输出信号以输出输出模拟信号。

公开(公告)号：US20140125505A1

公开(公告)日：2014-05-08

申请号：US14076492

申请日：2013-11-11

申请人： Kathrein-Werke KG

发明人： Udo Karthaus

IPC分类号： H03M3/00

CPC分类号： H03M3/30 ,  H03M3/508 ,  Y10T29/49002

摘要： A base band to frequency up-converter is described wherein the base band to frequency up-converter comprises a first input for receiving a first base band signal of first base band samples and a second input for receiving a second base band signal of second base band samples and an output for providing up-converted radio signal samples. The base-band to radio frequency up-converter further comprises a phase converter for converting the first base band signal of first base band samples and the second base band signal of second base band samples into a first intermediate signal of first intermediate samples, a second intermediate signal of second intermediate samples, and a third intermediate signal of third intermediate samples. The intermediate samples are then up-converted into radio signal samples.

摘要翻译： 描述了一种基带到上变频器，其中基带到上变频器包括用于接收第一基带采样的第一基带信号的第一输入端和用于接收第二基带的第二基带信号的第二输入端 样本和用于提供上变频无线电信号样本的输出。 基带到射频上变频器还包括相位转换器，用于将第一基带样本的第一基带信号和第二基带样本的第二基带信号转换为第一中间样本的第一中间信号，第二 第二中间样品的中间信号和第三中间样品的第三中间信号。 然后将中间样本上变频成无线电信号样本。

公开(公告)号：US20140086356A1

公开(公告)日：2014-03-27

申请号：US13701374

申请日：2012-10-26

申请人： LSI Corporation

发明人： Kameran Azadet ,  Chengzhou Li ,  Albert Molina ,  Joseph H. Othmer ,  Steven C. Pinault ,  Meng-Lin Yu ,  Joseph Willimas ,  Ramon Sanchez Perez ,  Jian-Guo Chen

IPC分类号： H04L25/02

CPC分类号： G06F9/3001 ,  G06F5/01 ,  G06F9/30036 ,  G06F17/15 ,  H03F1/0288 ,  H03F1/3241 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/336 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233 ,  H03H17/06 ,  H03M3/30 ,  H04B1/0003 ,  H04B1/0475 ,  H04B1/62 ,  H04B2001/0408 ,  H04L1/0054 ,  H04L25/02 ,  H04L25/03 ,  H04L25/03178 ,  H04L25/03216 ,  H04L25/4917 ,  H04L27/2334

摘要： Software Digital Front End (SoftDFE) signal processing techniques are provided. One or more digital front end (DFE) functions are performed on a signal in software by executing one or more specialized instructions on a processor to perform the one or more digital front end (DFE) functions on the signal, wherein the processor has an instruction set comprised of one or more of linear and non-linear instructions. A block of samples comprised of a plurality of data samples is optionally formed and the digital front end (DFE) functions are performed on the block of samples. The specialized instructions can include a vector convolution function, a complex exponential function, an xk function, a vector compare instruction, a vector max( ) instruction, a vector multiplication instruction, a vector addition instruction, a vector sqrt( ) instruction, a vector 1/x instruction, and a user-defined non-linear instruction.

摘要翻译： 提供软件数字前端（SoftDFE）信号处理技术。 通过在处理器上执行一个或多个专用指令对信号执行一个或多个数字前端（DFE）功能，对软件中的信号执行一个或多个数字前端（DFE）功能，其中处理器具有指令 由线性和非线性指令中的一个或多个组成。 可选地形成由多个数据样本组成的样本块，并且在样本块上执行数字前端（DFE）功能。 专门的指令可以包括向量卷积函数，复指数函数，xk函数，向量比较指令，向量max（）指令，向量乘法指令，向量加法指令，向量sqrt（）指令，向量 1 / x指令和用户定义的非线性指令。

公开(公告)号：US20140077984A1

公开(公告)日：2014-03-20

申请号：US14022182

申请日：2013-09-09

申请人： MEDIATEK INC.

发明人： Yun-Shiang Shu

IPC分类号： H03M3/00

CPC分类号： H03M3/30 ,  H03M3/37 ,  H03M3/458

摘要： A delta-sigma modulator has a delta-sigma modulation loop and a plurality of excess loop delay (ELD) adjustment circuits. The delta-sigma modulation loop converts an analog input into a digital output. The ELD adjustment circuits perform different ELD adjustments according to the digital output for jointly adjusting an ELD of the delta-sigma modulation loop. Besides, a delta-sigma modulation method includes at least the following steps: converting an analog input into a digital output through a delta-sigma modulation loop; and employing different ELD adjustment schemes for jointly adjusting an ELD of the delta-sigma modulation loop according to the digital output.

摘要翻译： Δ-Σ调制器具有Δ-Σ调制环路和多个过剩环路延迟（ELD）调节电路。 Δ-Σ调制环路将模拟输入转换为数字输出。 ELD调整电路根据数字输出执行不同的ELD调整，以共同调整Δ-Σ调制环路的ELD。 此外，Δ-Σ调制方法至少包括以下步骤：通过Δ-Σ调制环将模拟输入转换成数字输出; 并采用不同的ELD调整方案，以根据数字输出共同调整Δ-Σ调制环路的ELD。

公开(公告)号：US08653996B2

公开(公告)日：2014-02-18

申请号：US13685063

申请日：2012-11-26

申请人： Gabriel Banarie ,  Adrian Sherry

发明人： Gabriel Banarie ,  Adrian Sherry

IPC分类号： H03M3/00

CPC分类号： H03M3/30 ,  H03M1/00 ,  H03M1/0668 ,  H03M1/66 ,  H03M1/74 ,  H03M3/464

摘要： A sigma-delta analog-to-digital converter (“ΣΔ ADC”) may include a loop filter, ADC, a feedback digital-to-analog converter (“DAC”), and a control circuit. The feedback DAC may include several unit elements (resistors, capacitors, or current sources) that, ideally, are identical to each other but vary due to mismatch errors introduced during manufacture. Mismatch errors may introduce signal errors that generate undesirable noise frequencies and non-linearities in a ΣΔ ADC output signal. Embodiments of the present invention provide a stability corrected second order shuffler that allows for the shaping of the frequency response by the ΣΔ ADC to reduce the effect of the mismatch error between DAC unit elements. The second order shuffler may include accumulation correctors, to suppress saturation for accumulators within the shuffler. The suppression may compress the range of accumulation values for each accumulator while maintaining context for the values to stabilize operation of the second order shuffler.

摘要翻译： Σ-Δ模数转换器（“SigmaDelta ADC”）可以包括环路滤波器，ADC，反馈数模转换器（“DAC”）和控制电路。 反馈DAC可以包括理想地彼此相同但由于在制造期间引入的失配错误而变化的几个单元元件（电阻器，电容器或电流源）。 不匹配误差可能引入在SigmaDelta ADC输出信号中产生不良噪声频率和非线性的信号误差。 本发明的实施例提供了稳定性校正的二阶洗牌器，其允许通过SigmaDelta ADC对频率响应进行整形，以减少DAC单元元件之间的失配误差的影响。 第二级洗牌器可以包括累积校正器，以抑制洗牌器内的累加器的饱和。 抑制可以压缩每个累加器的累加值的范围，同时保持值的上下文以稳定二阶洗牌器的操作。

公开(公告)号：US20140015700A1

公开(公告)日：2014-01-16

申请号：US14028905

申请日：2013-09-17

申请人： FUJITSU LIMITED

发明人： Kazuaki OISHI

IPC分类号： H03M3/00

CPC分类号： H03M3/50 ,  H03M3/30 ,  H03M7/3022

摘要： A MASH sigma-delta modulator includes: parallel integration units in M stages configured to receive N pieces of data from a previous stage, to perform integral calculation in parallel; parallel differentiation units each configured to calculate a difference between neighboring overflows of the corresponding parallel integration unit of the integration part; and a parallel-to-serial conversion part configured to parallel-to-serial convert outputs from the differentiation part, wherein the parallel integration units receive pieces of input data in parallel, the parallel integration unit in each stage and the parallel differentiation unit in each stage perform integral calculation and differential calculation in each stage in one operation clock of a frequency 1/N times a master clock frequency, and the parallel-to-serial conversion part outputs the result of the parallel-to-serial conversion in synchronization with the master clock.

摘要翻译： MASHΣ-Δ调制器包括：M级并行整合单元，被配置为从前一级接收N条数据，并行执行积分计算; 每个差分单元被配置为计算积分部分的相应的并行积分单元的相邻溢出之间的差异; 以及并行到串行转换部分，其被配置为并行 - 串行转换来自所述微分部分的输出，其中所述并行整合单元并行地接收输入数据，每个级中的并行整合单元和每个中的并行微分单元 在主时钟频率的1 / N倍的一个操作时钟中的每个级中执行积分计算和差分计算，并行到串行转换部分与并行到串行转换的结果同步地输出 主时钟。

公开(公告)号：US20130271305A1

公开(公告)日：2013-10-17

申请号：US13995156

申请日：2011-09-30

申请人： Hyung Seok Kim ,  Yee W. Li ,  Ashoke Ravi ,  Hasnain Lakdawala

发明人： Hyung Seok Kim ,  Yee W. Li ,  Ashoke Ravi ,  Hasnain Lakdawala

IPC分类号： H03M3/00 ,  H03M1/78

CPC分类号： H03M3/50 ,  G09G3/3688 ,  H03M1/00 ,  H03M1/0863 ,  H03M1/12 ,  H03M1/747 ,  H03M1/785 ,  H03M1/808 ,  H03M3/30 ,  H03M3/502

摘要： An inverter-driven resistor-ladder digital-to-analog (DAC) converter includes a resistor-ladder network that comprises a resistor for each bit signal of a multi-bit input signal. Each resistor of the resistor-ladder network comprises an input end and an output end. The input end of each resistor is coupled to a corresponding bit signal of the multi-bit input signal, and the output end of each resistor is coupled to an output node of the resistor-ladder network. An output voltage is generated at the output node that is based on the multi-bit input signal. In one exemplary embodiment, the multi-bit input signal is a sigma-delta (ΣΔ) modulated multi-bit input signal. In another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are related by a binary weighting. In still another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are substantially equal.

摘要翻译： 逆变器驱动的电阻梯形数模（DAC）转换器包括一个电阻梯形网络，包括一个多位输入信号的每个位信号的电阻。 电阻梯形网络的每个电阻器包括输入端和输出端。 每个电阻器的输入端耦合到多位输入信号的对应位信号，并且每个电阻器的输出端耦合到电阻梯形网络的输出节点。 在输出节点处产生基于多位输入信号的输出电压。 在一个示例性实施例中，多位输入信号是Σ-Δ（SigmaDelta）调制的多位输入信号。 在另一示例性实施例中，电阻梯形网络的电阻器的电阻值通过二进制加权相关。 在又一示例性实施例中，电阻梯形网络的电阻器的电阻值基本相等。

公开(公告)号：US20130207820A1

公开(公告)日：2013-08-15

申请号：US13715005

申请日：2012-12-14

申请人： Roberto S. MAURINO ,  Colin G. LYDEN

发明人： Roberto S. MAURINO ,  Colin G. LYDEN

IPC分类号： H03M3/00

CPC分类号： H03M3/30 ,  H03M3/328 ,  H03M3/422

摘要： A sigma delta modulator may include a loop filter and an adder configured to accept an output of the loop filter and a dither input signal. The adder may be further configured to combine the output of the loop filter and the dither input signal into a combined output signal. The sigma delta modulator may further include a quantizer configured to accept the combined output signal from the adder, and quantize the combined signal into a quantizer output signal. The sigma delta modulator may further include a first subtractor configured to accept the quantizer output signal and subtract the dither input signal from the quantizer output signal.

摘要翻译： Σ-Δ调制器可以包括环路滤波器和被配置为接受环路滤波器的输出和抖动输入信号的加法器。 加法器可以被进一步配置为将环路滤波器的输出和抖动输入信号组合成组合的输出信号。 Σ-Δ调制器还可以包括量化器，其被配置为接受来自加法器的组合输出信号，并将组合信号量化为量化器输出信号。 Σ-Δ调制器还可以包括：第一减法器，被配置为接受量化器输出信号，并从量化器输出信号中减去抖动输入信号。