公开(公告)号：US08571825B2

公开(公告)日：2013-10-29

申请号：US13617749

申请日：2012-09-14

申请人： Peter Anton Habitz ,  Jinjun Xiong ,  Vladimir Zolotov

发明人： Peter Anton Habitz ,  Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G01R31/3181 ,  G06F11/30

CPC分类号： G01R31/31718 ,  G01R31/31725 ,  G06F17/5031 ,  G06F2217/84

摘要： A method of integrated circuit (IC) disposition includes the steps of determining one or more disposition criteria based at least in part on statistical timing of a given IC design; and determining whether a given IC according to the given IC design satisfies the one or more disposition criteria based at least in part on one or more measurements of at least one test structure.

摘要翻译： 集成电路（IC）配置的方法包括至少部分地基于给定IC设计的统计定时来确定一个或多个处置标准的步骤; 以及至少部分地基于至少一个测试结构的一个或多个测量来确定根据给定IC设计的给定IC是否满足所述一个或多个处置标准。

公开(公告)号：US08548773B2

公开(公告)日：2013-10-01

申请号：US12607576

申请日：2009-10-28

申请人： Junqiang Shang ,  Liang Zhang ,  Yong Wang ,  Xin Liu

发明人： Junqiang Shang ,  Liang Zhang ,  Yong Wang ,  Xin Liu

IPC分类号： G06F11/30 ,  H03L7/06

CPC分类号： G01R31/31718 ,  G01R31/31725

摘要： A voltage controlled delay line (VCDL) for measuring the maximum speed of a chip includes a first input configured to receive a reference clock signal, a first output configured to output an output clock signal, and a second input configured to receive a phase error signal representing a phase delay between the reference and output clock signals. A register stores a delay code applied by the VCDL to the reference clock signal to delay the reference clock signal to generate the output clock signal. The delay code is adjusted according to the phase error signal until the phase delay is equal to a predetermined value. A second output is coupled to an interface that reads the delay code from the register and outputs the delay code to automated testing equipment when the phase delay is equal to the predetermined value. The outputted delay code corresponds to the maximum chip speed.

摘要翻译： 用于测量芯片的最大速度的电压控制延迟线（VCDL）包括被配置为接收参考时钟信号的第一输入，被配置为输出输出时钟信号的第一输出和被配置为接收相位误差信号的第二输入 表示参考和输出时钟信号之间的相位延迟。 寄存器将由VCDL施加的延迟码存储到参考时钟信号以延迟参考时钟信号以产生输出时钟信号。 根据相位误差信号调整延迟码，直到相位延迟等于预定值。 当相位延迟等于预定值时，第二输出耦合到从寄存器读取延迟码并将延迟代码输出到自动测试设备的接口。 输出的延迟代码对应于最大芯片速度。

公开(公告)号：US08539423B2

公开(公告)日：2013-09-17

申请号：US13649996

申请日：2012-10-11

申请人： Agere Systems LLC

发明人： Joseph J. Jamann ,  James C. Parker ,  Vishwas M. Rao

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G01R31/31725 ,  G06F1/04 ,  G06F1/26 ,  G06F1/3203 ,  G06F17/5081 ,  H03K19/215

摘要： One aspect provides a method of designing an integrated circuit. In one embodiment, the method includes: (1) generating a functional design for the integrated circuit, (2) determining performance objectives for the integrated circuit, (3) determining an optimization target voltage for the integrated circuit, (4) determining whether the integrated circuit needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the integrated circuit is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional integrated circuit design that meets the performance objectives by employing standardized data created by designing at least one representative benchmark circuit, and (6) performing a timing signoff of the layout at the optimization target voltage.

摘要翻译： 一方面提供一种设计集成电路的方法。 在一个实施例中，该方法包括：（1）产生集成电路的功能设计，（2）确定集成电路的性能目标，（3）确定集成电路的优化目标电压，（4） 集成电路需要电压缩放来实现优化目标电压下的性能目标，如果是，采用静态电压缩放或自适应电压缩放，（5）使用优化目标电压从功能上合成布局 集成电路设计，通过采用通过设计至少一个代表性基准电路创建的标准化数据来满足性能目标，以及（6）在优化目标电压下执行布局的定时签发。

公开(公告)号：US08539327B2

公开(公告)日：2013-09-17

申请号：US13153681

申请日：2011-06-06

申请人： Yuuki Ogata

发明人： Yuuki Ogata

IPC分类号： G06F11/00 ,  H03M13/00

CPC分类号： G06F11/26 ,  G01R31/31725

摘要： A semiconductor circuit for testing a logic circuit, the semiconductor circuit including: an exclusive OR circuit receiving an input testing signal to a circuit under testing and a output testing signal from the circuit under testing; a multiplexer receiving a result signal output from the exclusive OR circuit and a clock signal; and a flip-flop storing a logical value represented by a captured signal in synchronization with a multiplexed signal output from the multiplexer, the captured signal being selected from a entered signal (I) and a data signal that is output from another semiconductor circuit for testing.

摘要翻译： 一种用于测试逻辑电路的半导体电路，所述半导体电路包括：异或电路，其将待测电路的输入测试信号和来自被测电路的输出测试信号接收到输入测试信号; 接收从异或电路输出的结果信号和时钟信号的多路复用器; 以及触发器，其与从多路复用器输出的多路复用信号同步地存储由捕获信号表示的逻辑值，所捕获的信号从输入的信号（I）和从另一半导体电路输出的数据信号中进行测试 。

公开(公告)号：US08531196B1

公开(公告)日：2013-09-10

申请号：US12365147

申请日：2009-02-03

申请人： Jaydev Amit Shelat ,  Zunhang Yu Kasnavi ,  Dhananjay Srinivasa Raghavan

发明人： Jaydev Amit Shelat ,  Zunhang Yu Kasnavi ,  Dhananjay Srinivasa Raghavan

IPC分类号： G01R31/3187 ,  G01R31/26 ,  G01R31/28

CPC分类号： G01R31/2884 ,  G01R31/2831 ,  G01R31/31725

摘要： Programmable delay test circuitry is provided for testing a circuit under test on an integrated circuit. Delay test circuitry may use logic circuitry to output an error signal when a delay time provided by the circuit under test is greater than a characteristic time that may be programmed into the programmable delay test circuitry. Programmable delay test circuitry may use a logic gate to provide a pulse that has a pulse width equal to the delay of the delay circuitry. Programmable delay test circuitry may contain a programmable load that may be programmed to have a characteristic time. Programmable delay test circuitry may assert an error signal when the delay time is greater than the characteristic time of the test circuitry.

摘要翻译： 提供可编程延迟测试电路，用于在集成电路上测试被测电路。 当被测电路提供的延迟时间大于可编程到可编程延迟测试电路中的特征时间时，延迟测试电路可以使用逻辑电路来输出误差信号。 可编程延迟测试电路可以使用逻辑门来提供具有等于延迟电路的延迟的脉冲宽度的脉冲。 可编程延迟测试电路可以包含可编程为具有特征时间的可编程负载。 当延迟时间大于测试电路的特征时间时，可编程延迟测试电路可以断言错误信号。

公开(公告)号：US20130232387A1

公开(公告)日：2013-09-05

申请号：US13851587

申请日：2013-03-27

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Lee D. Whetsel

IPC分类号： G01R31/3177

CPC分类号： G01R31/31723 ,  G01R31/31722 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318572 ,  G06F11/261 ,  G06F11/267 ,  G06F11/27 ,  G06F11/3466

摘要： An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

公开(公告)号：US20130193999A1

公开(公告)日：2013-08-01

申请号：US13810609

申请日：2011-07-13

申请人： Matthew Turnquist ,  Lauri Koskinen ,  Jani Mäkipää ,  Erkka Laulainen

发明人： Matthew Turnquist ,  Lauri Koskinen ,  Jani Mäkipää ,  Erkka Laulainen

IPC分类号： H03K19/003

CPC分类号： H03K19/003 ,  G01R31/31725 ,  H03K3/012 ,  H03K3/0375

摘要： A sequential circuit with transition error detector including a sequential element with an input that is asserted to the output during the second clock phase of a two phase clock signal, a transition error detector coupled to the sequential element input to assert an error signal if a transition occurs at the sequential element input during the second clock phase but not to assert during the first clock phase, wherein a transition error detection circuit comprises a current mode circuit as a detection circuit for transition timing error detection from signals derived from the sequential element clock signal and input signals.

摘要翻译： 具有过渡误差检测器的顺序电路包括具有输入的顺序元件，该输入在两相时钟信号的第二时钟相位期间被输出到输出;转移误差检测器，耦合到顺序元件输入，以便在转换 在第二时钟相位期间在顺序元件输入处发生，而在第一时钟相位期间不进行断言，其中转换错误检测电路包括电流模式电路作为用于从顺序元件时钟信号导出的信号进行转换定时误差检测的检测电路 和输入信号。

公开(公告)号：US08442788B2

公开(公告)日：2013-05-14

申请号：US12198105

申请日：2008-08-25

申请人： Harry Hou ,  Takahiro Yamaguchi

发明人： Harry Hou ,  Takahiro Yamaguchi

IPC分类号： G06F19/00

CPC分类号： G01R31/31725 ,  G01R29/26 ,  G01R31/31937

摘要： Provided is a measurement apparatus that measures a signal under measurement, including a strobe timing generator that sequentially generates strobes arranged at substantially equal time intervals; a level comparing section that detects a signal level of the signal under measurement at a timing of each sequentially provided strobe; a capture memory that stores therein a data sequence of the signal levels sequentially detected by the level comparing section; a window function multiplying section that multiplies the data sequence by a window function; a frequency domain converting section that converts the data sequence multiplied by the window function into a spectrum in the frequency domain; and an instantaneous phase noise calculating section that calculates instantaneous phase noise on a time axis of the signal under measurement, based on the spectrum.

摘要翻译： 提供一种测量测量信号的测量装置，包括顺序地产生以基本相等的时间间隔布置的选通的选通脉冲定时发生器; 电平比较部，其在每个顺序提供的选通脉冲的定时检测被测信号的信号电平; 捕获存储器，其中存储由所述电平比较部分顺序检测的信号电平的数据序列; 窗口函数乘法部分，用于将数据序列乘以窗口函数; 频域转换部分，其将与窗函数相乘的数据序列转换为频域中的频谱; 以及瞬时相位噪声计算部，其根据该频谱计算被测信号的时间轴上的瞬时相位噪声。

公开(公告)号：US20130093488A1

公开(公告)日：2013-04-18

申请号：US13459659

申请日：2012-04-30

申请人： Ravi Karapatti Ramaswami ,  Vasu P. Ganti ,  Anh Hoang

发明人： Ravi Karapatti Ramaswami ,  Vasu P. Ganti ,  Anh Hoang

IPC分类号： H03H11/26

CPC分类号： G01R31/31725 ,  G01R31/3187

摘要： A system and method for efficiently performing timing characterization of regions of an integrated circuit. An integrated circuit has monitors distributed in different physical regions across its die. Each monitor includes timing characterization and self-test circuitry. This circuitry includes one or more tunable delay lines used during timing measurements. The circuitry verifies the tunable delay lines are defect free prior to the timing measurements. If defects are detected, but tunable delay lines may still be used, a scaling factor may be generated for a failing tunable delay line. The scaling factor may be used during subsequent timing measurements to maintain a high accuracy for the measurements. The timing measurements may determine a particular physical region of the die provides fast or slow timing values. The resulting statistics of the timing measurements may be used to change an operational mode of the IC in at least the particular region.

摘要翻译： 一种用于有效地执行集成电路的区域的定时表征的系统和方法。 集成电路具有分布在其芯片上的不同物理区域中的监视器。 每个监视器包括时序表征和自检电路。 该电路包括在定时测量期间使用的一个或多个可调延迟线。 在定时测量之前，电路验证可调延迟线是无缺陷的。 如果检测到缺陷，但是仍然可以使用可调延迟线，则可能会为故障的可调延迟线产生缩放因子。 在随后的定时测量期间可以使用缩放因子以保持测量的高精度。 定时测量可以确定芯片的特定物理区域提供快速或慢速定时值。 所得到的定时测量统计可用于至少在特定区域中改变IC的操作模式。

公开(公告)号：US08405413B2

公开(公告)日：2013-03-26

申请号：US12861289

申请日：2010-08-23

申请人： Gary D. Carpenter ,  Alan J. Drake ,  Michael S. Floyd ,  Robert M. Senger

发明人： Gary D. Carpenter ,  Alan J. Drake ,  Michael S. Floyd ,  Robert M. Senger

IPC分类号： G01R31/3187

CPC分类号： G01R31/31725

摘要： A critical path monitor having selectable data output modes provides additional information about critical path delay variation. A pulse is propagated through a synthesized path representing a critical path in a functional logic circuit and a synthesized path delay is measured by a monitoring circuit that detects the arrival of an edge of the pulse at the output of the synthesized delay. The measured delay is provided as a real-time output and a processed result of the measured delay is processed according to a data output mode selected from multiple selectable output modes, thereby providing different information describing the real-time data about critical path delay, such as a range of edge positions corresponding to a variation of the critical path delay.

摘要翻译： 具有可选数据输出模式的关键路径监视器提供关于关键路径延迟变化的附加信息。 脉冲通过表示功能逻辑电路中的关键路径的合成路径传播，合成路径延迟由检测脉冲边缘在合成延迟的输出处的监控电路测量。 测量的延迟被提供为实时输出，并且根据从多个可选输出模式中选择的数据输出模式来处理测量的延迟的处理结果，从而提供描述关于关键路径延迟的实时数据的不同信息，例如 作为对应于关键路径延迟的变化的边缘位置的范围。