公开(公告)号：US20140106475A1

公开(公告)日：2014-04-17

申请号：US13730532

申请日：2012-12-28

Applicant: SHANGHAI HUALI MICROELECTRONICS CORPORATION

Inventor： Zaifeng TANG ,  Chao FANG ,  Yukun LV ,  HsuSheng CHANG

IPC: H01L21/66

CPC classification number: H01L22/26 ,  H01L21/28035 ,  H01L22/12

Abstract: A method for etching a polysilicon gate is disclosed, wherein the polysilicon gate includes an undoped polysilicon portion and a doped polysilicon portion that is situated on the undoped polysilicon portion. The method includes: obtaining a thickness of the undoped polysilicon portion and a thickness of the doped polysilicon portion by using an optical linewidth measurement device; and etching the undoped polysilicon portion and the doped polysilicon portion by using two respective steps with different parameters, respective etching time for the undoped polysilicon portion and the doped polysilicon portion of every wafer being adjusted in real time by using an advanced process control system. This method enables the doped and undoped polysilicon portions of each polysilicon gate on every wafer to have substantially consistent profiles between each other.

Abstract translation: 公开了蚀刻多晶硅栅极的方法，其中多晶硅栅极包括未掺杂多晶硅部分和位于未掺杂多晶硅部分上的掺杂多晶硅部分。 该方法包括：通过使用光学线宽测量装置获得未掺杂多晶硅部分的厚度和掺杂多晶硅部分的厚度; 并且通过使用具有不同参数的两个相应步骤蚀刻未掺杂多晶硅部分和掺杂多晶硅部分，通过使用先进的过程控制系统实时调整每个晶片的未掺杂多晶硅部分和掺杂多晶硅部分的相应蚀刻时间。 该方法使得每个晶片上的每个多晶硅栅极的掺杂和未掺杂的多晶硅部分之间具有基本一致的分布。

公开(公告)号：US08673768B2

公开(公告)日：2014-03-18

申请号：US13730103

申请日：2012-12-28

Applicant: Shanghai Huali Microelectronics Corporation

Inventor： Jingxun Fang ,  Chuanmin Zhang ,  Wei Zuo ,  Xiaogang Tong ,  Zhe Wang ,  Lei Deng ,  Jing Wen

IPC: H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/7684 ,  H01L21/3212 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fabrication method for improving surface planarity after tungsten chemical mechanical polishing (W-CMP) is disclosed. The method forms contact holes and dummy patterns by performing two respective photolithography-and-etching processes to ensure that the dummy patterns have a depth smaller than that of the contact holes. Then the method fills tungsten into the contact holes and dummy patterns and removes the redundant tungsten by a W-CMP process. With such a method, difference of wiring density between areas can be reduced by the dummy patterns, and hence a better surface planarity of the contact hole layer can be achieved. Besides, as the dummy patterns are formed in a pre-metal dielectric layer and their depth is well controlled, tungsten filled in the dummy patterns will not contact with the device area below the pre-metal dielectric layer, and thus will not affect the performance of the device.

Abstract translation: 公开了一种用于改善钨化学机械抛光（W-CMP）之后的表面平面度的制造方法。 该方法通过执行两个相应的光刻和蚀刻工艺来形成接触孔和虚拟图案，以确保虚拟图案的深度小于接触孔的深度。 然后，该方法将钨填充到接触孔和虚拟图案中，并通过W-CMP工艺去除冗余钨。 通过这种方法，可以通过虚拟图案来减小区域之间的布线密度的差异，因此可以实现接触孔层的更好的表面平面度。 此外，由于在预金属介电层中形成虚拟图案并且其深度被很好地控制，填充在虚设图案中的钨将不会与预金属介电层下方的器件区域接触，因此不会影响性能 的设备。

公开(公告)号：US08659071B2

公开(公告)日：2014-02-25

申请号：US13721078

申请日：2012-12-20

Applicant: Shanghai Huali Microelectronics Corporation

Inventor： Zhi Tian

IPC: H01L29/66

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/518

Abstract: The invention provides a SONOS structure, a manufacturing method thereof and a semiconductor device with the SONOS structure. The SONOS structure comprises: a first tunneling oxide layer formed on a substrate, a charge storage silicon nitride layer, a second silicon oxide layer, a thin graded silicon nitride layer having graded Si/N content formed on the second silicon oxide layer, a third silicon oxide layer formed on the thin graded silicon nitride layer, and a polysilicon control gate. The Si/N content ratio of the silicon nitride of the thin graded silicon nitride layer increases gradually, wherein the silicon nitride of the graded silicon nitride layer closer to the second silicon oxide layer contains higher nitride content, and the silicon nitride of the graded silicon nitride layer closer to the third silicon oxide layer contains higher silicon content.

Abstract translation: 本发明提供了SONOS结构，其制造方法和具有SONOS结构的半导体器件。 SONOS结构包括：形成在衬底上的第一隧道氧化物层，电荷存储氮化硅层，第二氧化硅层，在第二氧化硅层上形成的具有分级的Si / N含量的薄梯度氮化硅层， 形成在薄梯度氮化硅层上的氧化硅层和多晶硅控制栅极。 薄梯度氮化硅层的氮化硅的Si / N含量比逐渐增加，其中更靠近第二氧化硅层的梯度氮化硅层的氮化硅含有较高的氮化物含量，并且分级硅的氮化硅 更靠近第三氧化硅层的氮化物层含有较高的硅含量。

公开(公告)号：US20130344697A1

公开(公告)日：2013-12-26

申请号：US13730446

申请日：2012-12-28

Applicant: SHANGHAI HUALI MICROELECTRONICS CORPORATION

Inventor： Qiang XU

IPC: H01L21/311

CPC classification number: H01L21/31116 ,  H01L21/823807 ,  H01L21/82385

Abstract: A method of fabricating n-channel metal-oxide-semiconductor (NMOS) devices is disclosed, the method including: providing a substrate having a plurality of NMOS structures formed thereon; depositing a silicon nitride layer having a high tensile stress over the substrate; and sequentially exposing and dry etching a plurality of portions of the silicon nitride layer in an order of channel lengths of the plurality of NMOS structures such that each portion of the etched silicon nitride layer has a thickness proportional to the channel length of its corresponding NMOS structure. Compared to a conventional method, the above fabrication method of NMOS devices can achieve uniform performance adjustment of NMOS devices after a silicon nitride layer with a high tensile stress is deposited.

Abstract translation: 公开了一种制造n沟道金属氧化物半导体（NMOS）器件的方法，该方法包括：提供其上形成有多个NMOS结构的衬底; 在衬底上沉积具有高拉伸应力的氮化硅层; 并以多个NMOS结构的沟道长度的顺序顺序地曝光和干蚀刻氮化硅层的多个部分，使得蚀刻的氮化硅层的每个部分具有与其对应的NMOS结构的沟道长度成比例的厚度 。 与常规方法相比，上述NMOS器件的制造方法可以在沉积高拉伸应力的氮化硅层之后实现NMOS器件的均匀性能调整。

公开(公告)号：US20130181279A1

公开(公告)日：2013-07-18

申请号：US13721068

申请日：2012-12-20

Applicant: Shanghai Huali Microelectronics Corporation

Inventor： Zhi TIAN ,  Xinyun XIE

IPC: H01L29/792 ,  H01L21/28

CPC classification number: H01L29/792 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L29/40117 ,  H01L29/66833

Abstract: The invention provides an SONOS structure and a manufacturing method thereof The manufacturing method comprises: forming a tunneling oxide layer on a substrate; depositing a Si-rich silicon nitride layer above the tunneling oxide layer, wherein the Si/N content ratio of the Si-rich silicon nitride layer is constant; depositing a graded silicon nitride layer having graded silicon content above the Si-rich silicon nitride layer; and depositing a blocking oxide layer; wherein the silicon content of the graded silicon nitride layer is reduced in the direction from the Si-rich silicon nitride layer to the blocking oxide layer. According to the present invention, the Si-rich silicon nitride layer provides shallower trapping levels, which is beneficial to trap the charges and improve the programming and erasing speed. Furthermore, the charge retention time increases due to the constrained charges in the deep trapping levels, thus the reliability of the device enhances.

Abstract translation: 本发明提供一种SONOS结构及其制造方法。其制造方法包括：在基板上形成隧道氧化物层; 在隧穿氧化物层上沉积富Si硅氮化物层，其中富Si硅氮化物层的Si / N含量比是恒定的; 在富Si硅氮化物层上沉积具有分级硅含量的梯度氮化硅层; 和沉积阻挡氧化物层; 其中梯度氮化硅层的硅含量在从富Si硅氮化物层到阻挡氧化物层的方向上减小。 根据本发明，富Si硅氮化物层提供较浅的俘获电平，这有利于捕获电荷并提高编程和擦除速度。 此外，由于在深陷阱电平中受限的电荷，电荷保留时间增加，因此器件的可靠性增强。

公开(公告)号：US20130138415A1

公开(公告)日：2013-05-30

申请号：US13690245

申请日：2012-11-30

Applicant: Shanghai Huali Microelectronics Corporation

Inventor： Meimei GU ,  Jian LI ,  Jingchun ZHANG

IPC: G06F17/18

CPC classification number: G06F17/18 ,  H01L22/12 ,  H01L22/20

Abstract: The present invention provides a method and model for monitoring the pretreatment process of a low-k block layer. The method comprises measuring film parameters of the film formed on the silicon substrate after applying the pretreatment process for different time periods; creating a statistical process control curve according to the film parameters; setting a SPC control limit; determining the pretreatment process normal when the data point of measurement in the SPC curve is within the control limit while determining the pretreatment process abnormal when the data point of measurement in the SPC curve exceeds the control limit. According to the present invention, the failure of the pretreatment process can be prevented to improve the product reliability and stability.

Abstract translation: 本发明提供了一种用于监测低k阻挡层的预处理过程的方法和模型。 该方法包括在施加预处理过程不同时间段之后测量在硅衬底上形成的膜的膜参数; 根据电影参数创建统计过程控制曲线; 设置SPC控制限制; 当SPC曲线中的数据测量点在控制极限内时，当确定预处理过程异常时，在SPC曲线中的数据测量点处于控制极限内时，确定预处理过程正常。 根据本发明，可以防止预处理过程的故障，从而提高产品的可靠性和稳定性。

公开(公告)号：US20130137196A1

公开(公告)日：2013-05-30

申请号：US13687148

申请日：2012-11-28

Applicant: Shanghai Huali Microelectronics Corporation

Inventor： Hunglin CHEN ,  Kai WANG ,  Lujun ZHU ,  Qiliang NI ,  Yin LONG ,  Mingsheng GUO

IPC: H01L21/66

CPC classification number: H01L22/10 ,  H01L22/14 ,  H01L22/20

Abstract: The invention provides a method for monitoring devices in semiconductor process comprising: Step a, designing a sampling plan with fixed sample size before the beginning of the semiconductor process; Step b, determining whether to sample the wafers according to the sampling plan and dispatching the wafers to be sampled to each process device before the beginning of the process step, wherein the process device is used for performing the process step; Step c, performing the process step; Step d, sampling the wafers according to the sampling plan, and performing in-line inspection to the sampled wafers according to the sampling results; Step e, repeating Step b to Step d until all the process steps are completed; Step f, performing e-test to all the wafers. According to the method, the potential risk during the semiconductor process can be minimized through the coordination of the sampling plan and the dynamic risk flag.

Abstract translation: 本发明提供了一种用于监测半导体工艺中的器件的方法，包括：步骤a，在半导体工艺开始之前设计具有固定样品尺寸的采样方案; 步骤b，确定是否根据采样计划对晶片进行采样，并且在开始处理步骤之前将要采样的晶片调度到每个处理装置，其中处理装置用于执行处理步骤; 步骤c，执行处理步骤; 步骤d，根据采样方案对晶片进行采样，并根据采样结果对采样晶片进行在线检测; 步骤e，重复步骤b至步骤d，直到所有处理步骤完成; 步骤f，对所有晶片执行电子测试。 根据该方法，可以通过协调采样计划和动态风险标志来最小化半导体过程中的潜在风险。

公开(公告)号：US20130067423A1

公开(公告)日：2013-03-14

申请号：US13339411

申请日：2011-12-29

Applicant: Fang WEI ,  Chenming ZHANG

Inventor： Fang WEI ,  Chenming ZHANG

IPC: G06F17/50

CPC classification number: G03F7/70441 ,  G03F1/36

Abstract: The present invention relates to the field of semiconductor manufacturing, and particularly to a method of making Optical Proximity Correction to an original gate photomask pattern based on different substrate areas. The present invention discloses a method of making OPC to an original gate photomask pattern based on different substrate areas, which makes correction to gate photomask pattern dimension on the AA and to gate photomask pattern dimension on the STI respectively by creating two different optical proximity effect models of the gate, so as to control the finally imaged gate photomask pattern dimensions more accurately; moreover, the error of the correction result of the gate spacing dimension on the STI can be reduced by 4% by separating the patterns and using the gate model based on the STI, so as to avoid the spacing dimension error when the photolithography exposure conditions vary.

Abstract translation: 本发明涉及半导体制造领域，特别涉及一种基于不同衬底区域对原始栅光掩模图案进行光学邻近校正的方法。 本发明公开了一种基于不同衬底区域将OPC制作到原始栅光掩模图案的方法，其通过创建两个不同的光学邻近效应模型来分别校正在AA上的栅极光掩模图案尺寸和STI上的栅极光掩模图案尺寸 以便更精确地控制最终成像的门光掩模图案尺寸; 此外，通过分离图案并使用基于STI的栅极模型，STI上的栅极间隔尺寸的校正结果的误差可以减小4％，以便当光刻曝光条件变化时避免间隔尺寸误差 。

公开(公告)号：US12212319B2

公开(公告)日：2025-01-28

申请号：US18231851

申请日：2023-08-09

Applicant: Shanghai Huali Microelectronics Corporation

Inventor： Yu Jia ,  Yifei Qian

IPC: H03K19/0185 ,  H03K17/22 ,  H03K17/687

Abstract: The present application discloses a power-on-reset circuit, which optimizes a hysteresis circuit and a reset signal generation circuit, and introduces a seventh PMOS transistor as a switch transistor to achieve the differentiation of control voltages at a gate end of a first NMOS transistor during powering-on and off. A voltage rise detection point is determined by a partial voltage of a resistor during powering-on, while a voltage fall detection point is directly determined by a power supply voltage during powering-off. Such differentiation may achieve a significant separation between the voltage rise detection point and the voltage fall detection point, reducing the voltage fall detection point to near a threshold voltage of the first NMOS transistor, and meeting the demand for a lower voltage fall detection point, which is consistent with a practical application of the power-on-reset circuit in an MCU.

公开(公告)号：US11980032B2

公开(公告)日：2024-05-07

申请号：US17352451

申请日：2021-06-21

Applicant: Shanghai Huali Microelectronics Corporation

Inventor： Xiaoliang Tang ,  Naoki Tsuji ,  Haoyu Chen ,  Hua Shao

IPC: H10B43/35

CPC classification number: H10B43/35

Abstract: The present application discloses a method for manufacturing a SONOS memory, including: providing a substrate, wherein a first transistor gate of the SONOS memory and a first layer used for forming a second transistor gate are formed on the substrate; forming a patterned second layer on the upper surface of the first layer, wherein the second layer exposes the first layer corresponding to the outer side of the second transistor gate; performing first etching on the first layer exposed by the second layer; removing the second layer; and performing second etching on the first layer to form the second transistor gate. The present application also discloses a SONOS memory. The present application can form a vertical structure outside a selective transistor and a storage transistor, thus forming a vertical side wall in the subsequent process, so as to improve the performance of the device.