公开(公告)号：US08698196B2

公开(公告)日：2014-04-15

申请号：US13170965

申请日：2011-06-28

Applicant: Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Jun Hu ,  Wayne F. Eng

Inventor： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Jun Hu ,  Wayne F. Eng

IPC: H01L29/66 ,  H01L29/06

CPC classification number: H01L29/66113 ,  H01L21/265 ,  H01L21/76224 ,  H01L21/822 ,  H01L27/0248 ,  H01L27/0255

Abstract: A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.

公开(公告)号：US08674480B2

公开(公告)日：2014-03-18

申请号：US12966078

申请日：2010-12-13

Applicant: Tzuyin Chiu ,  TungYuan Chu ,  Wensheng Qian ,  YungChieh Fan ,  Jun Hu ,  Donghua Liu ,  Yukun Lv

Inventor： Tzuyin Chiu ,  TungYuan Chu ,  Wensheng Qian ,  YungChieh Fan ,  Jun Hu ,  Donghua Liu ,  Yukun Lv

IPC: H01L29/66

CPC classification number: H01L21/76232 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0657 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/7322 ,  H01L29/7378

Abstract: A high voltage bipolar transistor with shallow trench isolation (STI) comprises the areas of a collector formed by implanting first electric type impurities into active area and connected with pseudo buried layers at two sides; Pseudo buried layers which are formed by implanting high dose first type impurity through the bottoms of STI at two sides if active area, and do not touch directly; deep contact through field oxide to contact pseudo buried layers and pick up the collectors; a base deposited on the collector by epitaxial growth and in-situ doped by second electric type impurity, in which the intrinsic base touches local collector and extrinsic base is used for base pick-up; a emitter which is a polysilicon layer deposited on the intrinsic base and doped with first electric type impurities. This invention makes the depletion region of collector/base junction from 1D (vertical) distribution to 2D (vertical and lateral) distribution. The bipolar transistor's breakdown voltages are increased by only enlarge active critical dimension (CD). This is low-cost process.

Abstract translation: 具有浅沟槽隔离（STI）的高电压双极晶体管包括通过将第一电型杂质注入有源区并且在两侧与伪掩埋层连接而形成的集电极的区域; 伪埋层是通过在两侧的STI两侧植入高剂量第一类杂质而形成的，如果有活动区域，并且不直接接触; 通过场氧化物深接触接触伪埋层并拾取集电器; 通过外延生长沉积在集电体上并通过第二电型杂质原位掺杂的基极，其中本征基极接触局部集电极和外部基极用于基极拾取; 作为沉积在本征基底上并掺杂有第一电型杂质的多晶硅层的发射极。 本发明使集电极/基极结的耗尽区从1D（垂直）分布到2D（垂直和横向）分布。 双极晶体管的击穿电压仅通过增加主动临界尺寸（CD）来增加。 这是低成本的过程。

公开(公告)号：US20130113078A1

公开(公告)日：2013-05-09

申请号：US13613209

申请日：2012-09-13

Applicant: Donghua Liu ,  Wenting Duan ,  Wensheng Qian ,  Jun Hu ,  Jing Shi

Inventor： Donghua Liu ,  Wenting Duan ,  Wensheng Qian ,  Jun Hu ,  Jing Shi

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L29/94 ,  H01L29/66181

Abstract: A PIS capacitor in a SiGe HBT process is disclosed, wherein the PIS capacitor includes: a silicon substrate; a P-well and shallow trench isolations formed in the silicon substrate; a P-type heavily doped region formed in an upper portion of the P-well; an oxide layer and a SiGe epitaxial layer formed above the P-type heavily doped region; spacers formed on sidewalls of the oxide layer and the SiGe epitaxial layer; and contact holes for picking up the P-well and the SiGe epitaxial layer and connecting each of the P-well and the SiGe epitaxial layer to a metal wire. A method of manufacturing the PIS capacitor is also disclosed. The PIS capacitor of the present invention is manufactured by using SiGe HBT process, thus providing one more device option for the SiGe HBT process.

Abstract translation: 公开了SiGe HBT工艺中的PIS电容器，其中PIS电容器包括：硅衬底; 在硅衬底中形成的P阱和浅沟槽隔离; 形成在P阱的上部的P型重掺杂区域; 在P型重掺杂区域上形成氧化物层和SiGe外延层; 在氧化物层和SiGe外延层的侧壁上形成间隔物; 以及用于拾取P阱和SiGe外延层的接触孔，并将P阱和SiGe外延层中的每一个连接到金属线。 还公开了一种制造PIS电容器的方法。 通过使用SiGe HBT工艺制造本发明的PIS电容器，从而为SiGe HBT工艺提供了一种更多的器件选择。

公开(公告)号：US20130092981A1

公开(公告)日：2013-04-18

申请号：US13613151

申请日：2012-09-13

Applicant: Feng Han ,  Donghua Liu ,  Jun Hu ,  Wenting Duan ,  Jing Shi

Inventor： Feng Han ,  Donghua Liu ,  Jun Hu ,  Wenting Duan ,  Jing Shi

IPC: H01L29/737

CPC classification number: H01L29/0817 ,  H01L29/1004 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/7375

Abstract: A SiGe HBT having a position controlled emitter-base junction is disclosed. The SiGe HBT includes: a collector region formed of an N-doped active region; a base region formed on the collector region and including a base epitaxial layer, the base epitaxial layer including a SiGe layer and a capping layer formed thereon, the SiGe layer being formed of a SiGe epitaxial layer doped with a P-type impurity, the capping layer being doped with an N-type impurity; and an emitter region formed on the base region, the emitter region being formed of polysilicon. By optimizing the distribution of impurities doped in the base region, a controllable position of the emitter-base junction and adjustability of the reverse withstanding voltage thereof can be achieved, and thereby increasing the stability of the process and improving the uniformity within wafer.

Abstract translation: 公开了具有位置控制的发射极 - 基极结的SiGe HBT。 SiGe HBT包括：由N掺杂的有源区形成的集电极区域; 基底区域，形成在集电极区域上并且包括基底外延层，所述基底外延层包括SiGe层和形成在其上的覆盖层，所述SiGe层由掺杂有P型杂质的SiGe外延层形成，所述封盖 层掺杂有N型杂质; 以及形成在所述基极区上的发射极区域，所述发射极区域由多晶硅形成。 通过优化掺杂在基极区域中的杂质的分布，可以实现发射极 - 基极结的可控位置和其反向耐压的可调节性，从而提高了工艺的稳定性并提高了晶片内的均匀性。

公开(公告)号：US20130049750A1

公开(公告)日：2013-02-28

申请号：US13482554

申请日：2012-05-29

Applicant: Jinliang He ,  Yong Ouyang ,  Jun Hu ,  Shanxiang Wang ,  Shijie Ji ,  Rong Zeng ,  Bo Zhang ,  Zhanqing Yu

Inventor： Jinliang He ,  Yong Ouyang ,  Jun Hu ,  Shanxiang Wang ,  Shijie Ji ,  Rong Zeng ,  Bo Zhang ,  Zhanqing Yu

IPC: G01R33/09

CPC classification number: G01R15/205

Abstract: A giant magnetoresistance current sensor comprises an amorphous alloy magnetic ring having an air gap; a DC magnetic bias coil wound onto the amorphous alloy magnetic ring; a DC constant current source supplying power for the DC magnetic bias coil; a giant magnetoresistance chip disposed in the air gap and having positive and negative outputs; an instrument amplifier having a non-inverting input connected to the positive output of the giant magnetoresistance chip, and an inverting input connected to the negative output of the giant magnetoresistance chip; an operational amplifier having a non-inverting input connected to an output of the instrument amplifier; a voltage following resistance connected between an inverting input and an output of the operational amplifier; an analog to digital converter having an input connected to the output of the operational amplifier; and a digital tube display connected to an output of the analog to digital converter.

Abstract translation: 巨磁阻电流传感器包括具有气隙的非晶合金磁环; 缠绕在非晶合金磁环上的DC磁偏置线圈; 为直流磁偏置线圈供电的直流恒流源; 设置在气隙中并具有正和负输出的巨磁电阻芯片; 具有连接到巨磁电阻芯片的正输出的非反相输入的仪表放大器和连接到巨磁电阻芯片的负输出的反相输入; 运算放大器，其具有连接到所述仪表放大器的输出的非反相输入; 连接在运算放大器的反相输入和输出之间的电压跟随电阻; 模数转换器，具有连接到运算放大器的输出端的输入端; 以及连接到模数转换器的输出的数字管显示器。

公开(公告)号：US20130049102A1

公开(公告)日：2013-02-28

申请号：US13199381

申请日：2011-08-25

Applicant: Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Lingpeng Guan ,  Jun Hu

Inventor： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Lingpeng Guan ,  Jun Hu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/407 ,  H01L29/66712 ,  H01L29/78 ,  H01L29/7811

Abstract: This invention discloses a semiconductor power device formed in a semiconductor substrate comprises a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region. The semiconductor power device further comprises a body region, a source region and a gate disposed near the top surface of the semiconductor substrate and a drain disposed at a bottom surface of the semiconductor substrate. The semiconductor power device further comprises source trenches opened into the highly doped region filled with a conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises a buried field ring regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. In an alternate embodiment, the semiconductor power device further comprises doped regions surrounded the sidewalls of the source trenches and doped with a dopant of a same conductivity type of the buried field ring regions to function as a charge supply path.

Abstract translation: 本发明公开了一种形成在半导体衬底中的半导体功率器件，包括在轻掺杂区域顶部附近的半导体衬底的顶表面附近的高掺杂区域。 半导体功率器件还包括设置在半导体衬底的顶表面附近的体区，源区和栅极以及设置在半导体衬底的底表面处的漏极。 半导体功率器件还包括开口到高掺杂区域的源沟槽，填充有与顶表面附近的源区电接触的导电沟槽填充材料。 半导体功率器件还包括设置在源沟槽下方并且掺杂有与高掺杂区域具有相反导电性的掺杂剂的掩埋场环区域。 在替代实施例中，半导体功率器件还包括围绕源极沟槽的侧壁的掺杂区域，并掺杂有相同导电类型的掩埋场环区域的掺杂剂，用作电荷供应路径。

公开(公告)号：US20130001694A1

公开(公告)日：2013-01-03

申请号：US13170965

申请日：2011-06-28

Applicant: Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Jun Hu ,  Wayne F. Eng

Inventor： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Jun Hu ,  Wayne F. Eng

IPC: H01L23/60 ,  H01L21/336

CPC classification number: H01L29/66113 ,  H01L21/265 ,  H01L21/76224 ,  H01L21/822 ,  H01L27/0248 ,  H01L27/0255

Abstract: A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.

Abstract translation: 具有降低的钳位电压的低电容瞬态电压抑制器包括n +型衬底，衬底上的第一外延层，形成在第一外延层内的掩埋层，在第一外延层上形成的第二外延层，以及在第一外延层上形成的注入层 掩埋层下面的第一个外延层。 植入层延伸超过掩埋层。 第一沟槽位于掩埋层的边缘和植入层的边缘。 第二沟槽位于掩埋层的另一边缘并延伸到植入层中。 第三沟槽位于植入层的另一边缘。 每个沟槽衬有介电层。 一组源区形成在第二外延层的顶表面内。 沟渠和源区交替出现。 在第二外延层中形成一对注入区。

公开(公告)号：US08310934B2

公开(公告)日：2012-11-13

申请号：US13274653

申请日：2011-10-17

Applicant: Zhongming Hou ,  Jun Hu

Inventor： Zhongming Hou ,  Jun Hu

IPC: G08C15/00

CPC classification number: H04L47/266 ,  H04L47/30 ,  H04L69/14 ,  Y02D50/30

Abstract: A method for controlling information channel flow is provided according to the present invention, and includes: receiving information from multiple information channels of a data sending device, where the multiple information channels are divided into at least two channel groups, and a group number is set for the at least two channel groups respectively; determining an information channel requiring flow adjustment in the multiple information channels, and obtaining a group number of a channel group including the information channel requiring flow adjustment; generating flow operation information; and sending the flow operation information to the data sending device.

Abstract translation: 根据本发明提供一种用于控制信息信道流的方法，包括：从数据发送设备的多个信息信道接收信息，其中将多个信息信道划分为至少两个信道组，并且设置组号 分别用于至少两个信道组; 确定需要在多个信息信道中进行流量调整的信息信道，以及获得包括需要流量调整的信息信道的信道组的组号; 产生流动操作信息; 并将流程操作信息发送到数据发送装置。

公开(公告)号：US20110306539A1

公开(公告)日：2011-12-15

申请号：US13120146

申请日：2009-09-24

Applicant: Zhigang Shen ,  Jimmy Sung Lai Yun ,  Jun Hu ,  Arvind Jugade ,  Jiyao Zhang ,  Wenhao Chen ,  Zhe Wang ,  Lingyan Gao ,  Jian Feng Chen

Inventor： Zhigang Shen ,  Jimmy Sung Lai Yun ,  Jun Hu ,  Arvind Jugade ,  Jiyao Zhang ,  Wenhao Chen ,  Zhe Wang ,  Lingyan Gao ,  Jian Feng Chen

IPC: A61K38/02 ,  A61K31/216 ,  A61K31/513 ,  A61K31/546 ,  A61K38/13 ,  A61K31/357 ,  A61K31/57 ,  A61K31/7052 ,  A61K31/277 ,  A61K31/197 ,  A61K47/38 ,  A61K47/24 ,  A61K47/26 ,  A61K47/10 ,  A61P29/00 ,  A61K47/32 ,  A61P31/04 ,  A61P33/02 ,  A61P7/02 ,  A61P3/10 ,  A61P25/24 ,  A61P25/08 ,  A61P31/10 ,  A61P9/12 ,  A61P35/00 ,  A61P25/06 ,  A61P33/00 ,  A61P25/16 ,  A61P25/18 ,  A61P25/20 ,  A61P11/14 ,  A61P31/12 ,  A61P17/00 ,  A61P1/00 ,  A61P23/00 ,  A61P7/04 ,  A61P23/02 ,  A61P9/08 ,  A61K31/56

CPC classification number: A61K9/14 ,  A61K9/1623 ,  A61K9/1652 ,  A61K9/1694 ,  A61K9/2077 ,  B01J2/06 ,  B01J19/0093 ,  B01J2219/00788 ,  B01J2219/00889

Abstract: A process for making particles for delivery of drug nanoparticles is disclosed herein. The process comprises the steps of (a) forming a suspension of drug nanoparticles by mixing a precipitant solution with an anti-solvent solution under micro-mixing environment, where the formed nanoparticles have a narrow particle size distribution; (b) providing an excipient to at least one of the precipitant solution, the anti-solvent solution and the suspension of drug nanoparticles, the excipient being selected to maintain said drug nanoparticles in a dispersed state when in liquid form; and (c) drying the suspension of drug nanoparticles containing the excipient therein to remove solvent therefrom, wherein removal of the solvent causes the excipient to solidify and thereby form micro-sized matrix particles, each micro-sized particle being comprised of drug nanoparticles dispersed in a solid matrix of the excipient.

Abstract translation: 本文公开了用于制备用于递送药物纳米颗粒的颗粒的方法。 该方法包括以下步骤：（a）通过在微混合环境下将沉淀剂溶液与抗溶剂溶液混合形成药物纳米颗粒的悬浮液，其中所形成的纳米颗粒具有窄的粒度分布; （b）向沉淀剂溶液，抗溶剂溶液和药物纳米颗粒的悬浮液中的至少一种提供赋形剂，所述赋形剂被选择为当液体形式时将所述药物纳米颗粒维持在分散状态; 和（c）干燥其中含有赋形剂的药物纳米颗粒的悬浮液以从其中除去溶剂，其中去除溶剂导致赋形剂固化，从而形成微尺寸的基质颗粒，每个微尺寸颗粒由分散在 赋形剂的固体基质。

公开(公告)号：US20110156143A1

公开(公告)日：2011-06-30

申请号：US12975545

申请日：2010-12-22

Applicant: Tzuyin CHIU ,  TungYuan Chu ,  Wensheng Qian ,  YungChieh Fan ,  Donghua Liu ,  Jun Hu

Inventor： Tzuyin CHIU ,  TungYuan Chu ,  Wensheng Qian ,  YungChieh Fan ,  Donghua Liu ,  Jun Hu

IPC: H01L27/07 ,  H01L21/8249

CPC classification number: H01L29/732 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/7371

Abstract: This invention published a parasitic vertical PNP bipolar transistor in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process; the bipolar transistor comprises a collector, a base and an emitter. Collector is formed by active region with p-type ion implanting layer. It connects a p-type buried layer which formed in the bottom region of STI (Shallow Trench Isolation). The collector terminal connection is through the p-type buried layer and the adjacent active region. The base is formed by active region with n type ion implanting which is on the collector. Its connection is through the original p-type epitaxy layer after converting to n-type. The emitter is formed by the p-type epitaxy layer on the base region with heavy p-type doped. This invention also comprises the fabrication method of this parasitic vertical PNP bipolar in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process. And this PNP bipolar transistor can be used as the IO (Input/Output) device in high speed, high current and power gain BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) circuits. It also provides a device option with low cost.

Abstract translation: 本发明公开了BiCMOS（双极互补金属氧化物半导体）工艺中的寄生垂直PNP双极晶体管; 双极晶体管包括集电极，基极和发射极。 集电极由具有p型离子注入层的有源区形成。 它连接形成在STI底部区域（浅沟槽隔离）的p型掩埋层。 集电极端子连接通过p型掩埋层和相邻的有源区。 基极由在集电极上的n型离子注入的有源区形成。 其连接是通过原始的p型外延层转换为n型。 发射极由重p型掺杂的基极区上的p型外延层形成。 本发明还包括BiCMOS（双极互补金属氧化物半导体）工艺中该寄生垂直PNP双极的制造方法。 而这种PNP双极晶体管可以用作高速，大电流和功率增益BiCMOS（双极互补金属氧化物半导体）电路中的IO（输入/输出）器件。 它还提供低成本的设备选项。