公开(公告)号：US07436722B2

公开(公告)日：2008-10-14

申请号：US11761642

申请日：2007-06-12

申请人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

发明人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

IPC分类号： G11C7/00

CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.

摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置以隔离和耦合这些位线。位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电 到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。

公开(公告)号：US20070291564A1

公开(公告)日：2007-12-20

申请号：US11761642

申请日：2007-06-12

申请人： Hiroyuki MIZUNO ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

发明人： Hiroyuki MIZUNO ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

IPC分类号： G11C7/00

CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.

摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果：位线BL与连接到存储单元的局部位线LBL之间的开关装置用于隔离和耦合这些位线位线BL被预充电到VDL / 2的电压， 而局部位线LBL被预充电到VDL的电压。 VDL是位线BLA的最大幅度电压。读出放大器SA包括包括连接到位线BL的栅极的差分MOS对的第一电路和连接到用于全幅放大的局部位线LBL的第二电路， 用于保存数据。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。

公开(公告)号：US07254082B2

公开(公告)日：2007-08-07

申请号：US11363060

申请日：2006-02-28

申请人： Takao Watanabe ,  Kunio Uchiyama ,  Osamu Nishii ,  Naohiko Irie ,  Hiroyuki Mizuno

发明人： Takao Watanabe ,  Kunio Uchiyama ,  Osamu Nishii ,  Naohiko Irie ,  Hiroyuki Mizuno

IPC分类号： G11C8/00 ,  G11C5/14

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  G11C5/147 ,  G11C11/417 ,  Y02D10/171

摘要： When a leakage current of a circuit block under a non-use state is reduced by means of a power switch, frequent ON/OFF operations of the switch within a short time invite an increase of consumed power, on the contrary. Because a pre-heating time is necessary from turn-on of the switch till the circuit block becomes usable, control of the switch during an operation deteriorates a processing time of a semiconductor device. The switch is ON/OFF-controlled with a task duration time of a CPU core for controlling logic circuits and memory cores as a unit. After the switch is turned off, the switch is again turned on before termination of the task in consideration of the pre-heating time.

摘要翻译： 相反，当通过电源开关减小不使用状态下的电路块的漏电流时，短时间内开关频繁的接通/断开操作会引起消耗功率的增加。 由于开关的接通需要预热时间，直到电路块变得可用，所以在操作期间的开关的控制使半导体器件的处理时间变差。 该开关通过CPU核心的任务持续时间进行ON / OFF控制，用于将逻辑电路和存储器核心作为一个单元进行控制。 关闭开关后，考虑到预热时间，开关将在任务结束前再次打开。

公开(公告)号：US07242627B2

公开(公告)日：2007-07-10

申请号：US11363085

申请日：2006-02-28

申请人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

发明人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use latch type sense amplifier SA connected to the local bit line LBL.

摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置，用于这些位线的隔离和耦合。 位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。

公开(公告)号：US20070122210A1

公开(公告)日：2007-05-31

申请号：US11564653

申请日：2006-11-29

申请人： Kazuyuki Sato ,  Tadashi Shinohara ,  Shinji Kobayashi ,  Takao Watanabe ,  Nobuyoshi Kaima ,  Yuichiro Shukuya ,  Yoshiaki Kawai

发明人： Kazuyuki Sato ,  Tadashi Shinohara ,  Shinji Kobayashi ,  Takao Watanabe ,  Nobuyoshi Kaima ,  Yuichiro Shukuya ,  Yoshiaki Kawai

IPC分类号： G03G15/01

CPC分类号： G03G15/0105 ,  G03G15/1605 ,  G03G15/161 ,  G03G21/0011 ,  G03G2215/0161

摘要： In an image forming device, a correction unit corrects image formation operation based on a plurality of correction patterns. A pattern creation unit forms an electrostatic latent image of the correction patterns on a photoconductor and transferring the image to an intermediate transfer body to form the correction patterns thereon. A pattern detecting unit detects the correction patterns formed on the intermediate transfer body. A speed detecting unit detects a movement speed of the correction patterns on the intermediate transfer body are moved. A timing holding unit computes a set value of detection start timing for starting detection of each correction pattern to hold the set value. The correction unit is provided to determine, in advance of correcting image formation operation, a detection start timing based on the movement speed and the set value.

摘要翻译： 在图像形成装置中，校正单元基于多个校正图案校正图像形成操作。 图案生成单元在光电导体上形成校正图案的静电潜像，并将图像转印到中间转印体上以在其上形成校正图案。 图案检测单元检测形成在中间转印体上的校正图案。 速度检测单元检测中间转印体上的校正图案的移动速度。 定时保持单元计算检测开始定时的设定值，以开始检测每个校正图案以保持设定值。 提供校正单元，用于在校正图像形成操作之前，根据移动速度和设定值确定检测开始时刻。

公开(公告)号：US20070081380A1

公开(公告)日：2007-04-12

申请号：US11550735

申请日：2006-10-18

申请人： Bryan Atwood ,  Takao Watanabe

发明人： Bryan Atwood ,  Takao Watanabe

IPC分类号： G11C11/24

CPC分类号： G11C11/405

摘要： An object of the present invention is to reduce, during the standby time, the electric power caused by the leakage current flowing through a storage transistor in a 3-transistor dynamic cell. The present invention is configured as follows. Source electrodes of storage transistors in a plurality of 3-transistor dynamic cells constituting a memory array are connected, and a switch is provided between the source electrode and a power supply terminal. The leakage current during the standby time is interrupted by bringing the switch into a conducting state during the active time, and by bringing the switch into a nonconducting state during the standby time.

摘要翻译： 本发明的一个目的是在待机时间内减少由流过三晶体管动态单元中的存储晶体管的漏电流引起的电力。 本发明的结构如下。 构成存储器阵列的多个3晶体管动态单元中的存储晶体管的源极连接，并且在源电极和电源端子之间设置有开关。 在待机时间内，通过在开启时间内将开关置于导通状态，并在待机时间内将开关置于非导通状态，中断了待机时的漏电流。

公开(公告)号：US07199639B2

公开(公告)日：2007-04-03

申请号：US11410956

申请日：2006-04-26

申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takeshi Sakata ,  Takao Watanabe

发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takeshi Sakata ,  Takao Watanabe

IPC分类号： H03L5/00

CPC分类号： H03K19/0016 ,  H03K19/018521

摘要： A semiconductor device including a level converter (LSC) is disclosed. The level converter comprises a voltage-up circuit (LSC1) that operates on low voltage of power supply (VDD) and steps up voltage enough to drive the level converter and a level converter circuit (LSC2) that operates on high voltage of power supply (VDDQ). The voltage-up circuit is capable of constantly generating 2×VDD so that the level converter can convert a low voltage of power supply (VDD) below 1 V to VDDQ. This voltage-up circuit can be configured only with MOSFET transistors produced by thin oxide film deposition, thus enabling high-speed operation. To facilitate designing a circuit for preventing a leakage current from occurring in the level converter during sleep mode of a low-voltage-driven circuit (CB1), the level converter circuit (LSC2) includes a leak protection circuit (LPC) that exerts autonomous control for leak prevention, dispensing with external control signals.

摘要翻译： 公开了一种包括电平转换器（LSC）的半导体器件。 电平转换器包括在低电压（VDD）下工作并升压足以驱动电平转换器的升压电路（LSC 1）和在高电压功率下工作的电平转换器电路（LSC 2） 电源（VDDQ）。 升压电路能够持续产生2xVDD，因此电平转换器可将低于1 V的低电压电压（VDD）转换为VDDQ。 该升压电路只能由通过薄氧化膜沉积制造的MOSFET晶体管配置，从而实现高速操作。 为了便于设计用于防止低电压驱动电路（CB 1）的睡眠模式期间在电平转换器中发生漏电流的电路，电平转换器电路（LSC 2）包括泄漏保护电路（LPC） 自动控制防泄漏，外接控制信号。

公开(公告)号：US20060168865A1

公开(公告)日：2006-08-03

申请号：US10540944

申请日：2003-12-26

申请人： Takao Watanabe

发明人： Takao Watanabe

IPC分类号： A47G1/16

CPC分类号： H04N5/64 ,  F16M11/041 ,  F16M11/10 ,  F16M11/16 ,  F16M11/2014 ,  F16M13/02 ,  F16M2200/02 ,  G06F1/1601 ,  G06F1/1607 ,  H04N2005/4405 ,  Y10S248/918

摘要： In order to provide a display monitor, such as a thin design television or the like, in which its display unit is easily attachable and detachable from the stand structure and can be easily carried about, and where the place of installation of the display unit is not limited, a stand type thin design television includes a display unit (1), a joint body (15), a pillar (25) and a stand base (29). The joint body (15) is attached to the display unit (1) while the joint body (15) is free to be attached to and removed from the pillar (25) that is fixed to the stand base (29). In the first usage mode in which the pillar (25) and the stand base (29) are used, the joint (15) is inserted into the pillar (25). In the second usage mode in which the pillar (25) and the stand base (29) are not used, the joint body (15) itself is used as a stand.

摘要翻译： 为了提供诸如薄型设计电视等的显示监视器，其显示单元易于从支架结构安装和拆卸，并且可以容易地携带，并且显示单元的安装位置在 不限于此，台式薄设计电视机包括显示单元（1），接头体（15），支柱（25）和支架基座（29）。 接头本体（15）安装在显示单元（1）上，同时接头体（15）可自由地安装在固定于支架基座（29）上的支柱（25）上和从支座（25）上取下。 在使用支柱（25）和支架座（29）的第一使用模式中，接头（15）插入支柱（25）中。 在不使用支柱（25）和支架座（29）的第二使用模式中，接头本体（15）本身用作支架。

公开(公告)号：US07002856B2

公开(公告)日：2006-02-21

申请号：US11133232

申请日：2005-05-20

申请人： Takao Watanabe ,  Ryoichi Hori ,  Goro Kitsukawa ,  Yoshiki Kawajiri ,  Takayuki Kawahara ,  Kiyoo Itoh

发明人： Takao Watanabe ,  Ryoichi Hori ,  Goro Kitsukawa ,  Yoshiki Kawajiri ,  Takayuki Kawahara ,  Kiyoo Itoh

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C5/14 ,  G11C5/147 ,  G11C8/10 ,  G11C11/4094 ,  G11C11/413 ,  H03K5/08 ,  H03K17/693 ,  H03K19/00376 ,  H03K19/00384 ,  H03K19/017 ,  H03K19/01707 ,  H03K19/017518 ,  H03K19/09448 ,  H03K2217/0036

摘要： A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.

公开(公告)号：US06990002B2

公开(公告)日：2006-01-24

申请号：US10751402

申请日：2004-01-06

申请人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

发明人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

IPC分类号： G11C5/06

CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.

摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置，用于这些位线的隔离和耦合。 位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。