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    Artificial intelligence processor with three-dimensional stacked memory
    93.
    发明授权
    Artificial intelligence processor with three-dimensional stacked memory 有权

    公开(公告)号：US11139270B2

    公开(公告)日：2021-10-05

    申请号：US16357265

    申请日：2019-03-18

    Applicant: Kepler Computing Inc.

    Inventor： Sasikanth Manipatruni ,  Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Ramamoorthy Ramesh

    IPC: H01L25/065 ,  H01L23/525 ,  H01L23/00 ,  G06F9/50 ,  G11C7/10 ,  G11C11/419 ,  H01L27/11

    Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.

    LINEAR INPUT AND NON-LINEAR OUTPUT THRESHOLD LOGIC GATE
    94.
    发明申请
    LINEAR INPUT AND NON-LINEAR OUTPUT THRESHOLD LOGIC GATE 有权

    公开(公告)号：US20210203325A1

    公开(公告)日：2021-07-01

    申请号：US17129849

    申请日：2020-12-21

    Applicant: Kepler Computing, Inc.

    Inventor： Sasikanth Manipatruni ,  Robert Menezes ,  Yuan-Sheng Fang ,  Rajeev Kumar Dokania ,  Gaurav Thareja ,  Ramamoorthy Ramesh ,  Amrita Mathuriya

    IPC: H03K19/23

    Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.

    FERROELECTRIC CAPACITOR AND METHOD OF PATTERNING SUCH
    95.
    发明申请
    FERROELECTRIC CAPACITOR AND METHOD OF PATTERNING SUCH 有权

    公开(公告)号：US20210202689A1

    公开(公告)日：2021-07-01

    申请号：US16729267

    申请日：2019-12-27

    Applicant: Kepler Computing Inc.

    Inventor： Gaurav Thareja ,  Sasikanth Manipatruni ,  Rajeev Kumar Dokania ,  Ramamoorthy Ramesh ,  Amrita Mathuriya

    IPC: H01L49/02 ,  G11C11/22 ,  H01L27/11502

    Abstract: Ferroelectric capacitor is formed by conformably depositing a non-conductive dielectric over the etched first and second electrodes, and forming a metal cap or helmet over a selective part of the non-conductive dielectric, wherein the metal cap conforms to portions of sidewalls of the non-conductive dielectric. The metal cap is formed by applying physical vapor deposition at a grazing angle to selectively deposit a metal mask over the selective part of the non-conductive dielectric. The metal cap can also be formed by applying ion implantation with tuned etch rate. The method further includes isotopically etching the metal cap and the non-conductive dielectric such that non-conductive dielectric remains on sidewalls of the first and second electrodes but not on the third and fourth electrodes.

    Linear input and non-linear output threshold logic gate
    97.
    发明授权
    Linear input and non-linear output threshold logic gate 有权

    公开(公告)号：US11025254B1

    公开(公告)日：2021-06-01

    申请号：US16796824

    申请日：2020-02-20

    Applicant: Kepler Computing, Inc.

    Inventor： Sasikanth Manipatruni ,  Robert Menezes ,  Yuan-Sheng Fang ,  Rajeev Kumar Dokania ,  Gaurav Thareja ,  Ramamoorthy Ramesh ,  Amrita Mathuriya

    IPC: H03K19/00 ,  H03K19/20 ,  H03K19/23 ,  H01L49/02 ,  H03K19/01 ,  H03K19/003

    Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.

    Linear input and non-linear output majority logic gate
    98.
    发明授权
    Linear input and non-linear output majority logic gate 有权

    公开(公告)号：US11018672B1

    公开(公告)日：2021-05-25

    申请号：US16729275

    申请日：2019-12-27

    Applicant: Kepler Computing, Inc.

    Inventor： Sasikanth Manipatruni ,  Robert Menezes ,  Yuan-Sheng Fang ,  Rajeev Kumar Dokania ,  Gaurav Thareja ,  Ramamoorthy Ramesh ,  Amrita Mathuriya

    IPC: H03K19/00 ,  H03K19/20 ,  H03K19/23 ,  H01L49/02 ,  H03K19/003 ,  H03K19/01

    Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.

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