公开(公告)号：US20120124533A1

公开(公告)日：2012-05-17

申请号：US13358105

申请日：2012-01-25

Applicant: Steven H. VOLDMAN

Inventor： Steven H. VOLDMAN

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  H01L23/585 ,  H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and semiconductor structure to avoid latch-up is disclosed. The method includes identifying at least one high voltage device on a semiconductor chip, identifying a circuit on the semiconductor chip separated from the identified at least one high voltage device by a guard ring, evaluating the circuit for a latch-up condition, and when the latch-up condition occurs, adjusting the contact-circuit spacing in the circuit.

Abstract translation: 公开了一种避免闩锁的方法和半导体结构。 该方法包括识别半导体芯片上的至少一个高电压器件，识别半导体芯片上的由保护环与所识别的至少一个高电压器件分离的电路，评估该电路的闩锁状态，以及当 发生闩锁状态，调整电路中的接触电路间距。

公开(公告)号：US08108817B2

公开(公告)日：2012-01-31

申请号：US12030903

申请日：2008-02-14

Applicant: Steven H. Voldman

Inventor： Steven H. Voldman

IPC: G06F17/50 ,  H03K17/16 ,  H03K19/00 ,  H01L25/00 ,  H01L29/66 ,  H01L23/62

CPC classification number: G06F17/5045 ,  H01L23/585 ,  H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Method and semiconductor structure to avoid latch-up. Method includes identifying at least one high voltage device on a semiconductor chip, identifying a circuit on the semiconductor chip separated from the identified at least one high voltage device by a guard ring, evaluating the circuit for a latch-up condition, and when the latch-up condition occurs, adjusting the contact-circuit spacing in the circuit.

Abstract translation: 避免闭锁的方法和半导体结构。 方法包括识别半导体芯片上的至少一个高电压器件，通过保护环识别与所识别的至少一个高压器件分离的半导体芯片上的电路，评估电路的闩锁状态，以及当锁存器 发生上电状态，调整电路中的接触电路间距。

公开(公告)号：US20110227166A1

公开(公告)日：2011-09-22

申请号：US13150437

申请日：2011-06-01

Applicant: Steven H. VOLDMAN

Inventor： Steven H. VOLDMAN

IPC: H01L27/092 ,  G06F17/50

CPC classification number: H01L27/0921

Abstract: A structure for preventing latchup. The structure includes a latchup sensitive structure and a through wafer via structure bounding the latch-up sensitive structure to prevent parasitic carriers from being injected into the latch-up sensitive structure.

Abstract translation: 用于防止闩锁的结构。 该结构包括闭锁敏感结构和限制闩锁敏感结构的穿透晶片通孔结构，以防止寄生载流子注入到闩锁敏感结构中。

公开(公告)号：US20110227130A1

公开(公告)日：2011-09-22

申请号：US13150440

申请日：2011-06-01

Applicant: Xuefeng LIU ,  Robert M. RASSEL ,  Steven H. VOLDMAN

Inventor： Xuefeng LIU ,  Robert M. RASSEL ,  Steven H. VOLDMAN

IPC: H01L29/12 ,  H01L29/06

CPC classification number: H01L21/84 ,  H01L21/76243 ,  H01L21/76264 ,  H01L21/823807 ,  H01L21/8249 ,  H01L27/0635 ,  H01L27/0652 ,  H01L27/092 ,  H01L27/1203 ,  H01L27/1207

Abstract: Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions.

Abstract translation: 半导体结构和形成半导体结构的方法，更具体地涉及用于形成用于SOI / SiGe器件的SiGe和/或SiGeC掩埋层的结构和方法。 集成结构包括具有交替的Si和SiGe或SiGeC区域的不连续的掩埋层。 该结构还包括在Si和SiGe或SiGeC区域之间的界面处的隔离结构，以减少交替区域之间的缺陷。 器件与Si和SiGe或SiGeC区域相关联。

公开(公告)号：US20110198703A1

公开(公告)日：2011-08-18

申请号：US13095158

申请日：2011-04-27

Applicant: Phillip F. CHAPMAN ,  David S. COLLINS ,  Steven H. VOLDMAN

Inventor： Phillip F. CHAPMAN ,  David S. COLLINS ,  Steven H. VOLDMAN

IPC: H01L27/092 ,  H01L21/02

CPC classification number: H01L27/0921 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76898 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L23/481 ,  H01L27/092 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material.

Abstract translation: 一种制造半导体结构的方法包括：在衬底的背面形成沟槽; 在沟槽的表面上沉积掺杂剂; 在与沟槽相对的衬底的顶侧中形成浅沟槽隔离（STI）结构; 在基材中形成深井; 将掺杂剂扩散到深阱和衬底中; 在衬底中形成N阱和P阱; 并用导电材料填充沟槽。

公开(公告)号：US07989282B2

公开(公告)日：2011-08-02

申请号：US12411624

申请日：2009-03-26

Applicant: Steven H. Voldman

Inventor： Steven H. Voldman

IPC: H01L21/8238

CPC classification number: H01L27/0921

Abstract: A method and structure for preventing latchup. The structure includes a latchup sensitive structure and a through wafer via structure bounding the latch-up sensitive structure to prevent parasitic carriers from being injected into the latch-up sensitive structure.

Abstract translation: 一种防止闭锁的方法和结构。 该结构包括闭锁敏感结构和限制闩锁敏感结构的穿透晶片通孔结构，以防止寄生载流子注入到闩锁敏感结构中。

公开(公告)号：US20100244187A1

公开(公告)日：2010-09-30

申请号：US12411612

申请日：2009-03-26

Applicant: Steven H. VOLDMAN

Inventor： Steven H. VOLDMAN

IPC: H01L29/861 ,  H01L21/02

CPC classification number: H01L27/0248 ,  H01L23/481 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/585 ,  H01L23/60 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: The present invention generally relates to a circuit structure and a method of manufacturing a circuit, and more specifically to an electrostatic discharge (ESD) circuit with a through wafer via structure and a method of manufacture. An ESD structure includes an ESD active device and at least one through wafer via structure providing a low series resistance path for the ESD active device to a substrate. An apparatus includes an input, at least one power rail and an ESD circuit electrically connected between the input and the at least one power rail, wherein the ESD circuit comprises at least one through wafer via structure providing a low series resistance path to a substrate. A method, includes forming an ESD active device on a substrate, forming a ground plane on a backside of the substrate and forming at least one through wafer via electrically connected to a negative power supply of the ESD active device and the ground plane to provide a low series resistance path to the substrate.

Abstract translation: 本发明一般涉及一种电路结构及其制造方法，更具体地说涉及一种具有贯通晶片通孔结构和制造方法的静电放电（ESD）电路。 ESD结构包括ESD有源器件和至少一个贯穿晶片通孔结构，其提供用于ESD有源器件到衬底的低串联电阻通路。 一种装置包括输入，至少一个电源轨和ESD电路，电连接在输入和至少一个电源轨之间，其中ESD电路包括提供到衬底的低串联电阻路径的至少一个贯通晶片通孔结构。 一种方法，包括在衬底上形成ESD有源器件，在衬底的背面形成接地平面，并通过电连接到ESD有源器件和接地平面的负电源，形成至少一个通过晶片，从而提供 低的串联电阻路径到基板。

公开(公告)号：US07732293B2

公开(公告)日：2010-06-08

申请号：US12185140

申请日：2008-08-04

Applicant: Steven H. Voldman

Inventor： Steven H. Voldman

IPC: H01L21/8222

CPC classification number: H01L29/66136 ,  H01L27/0255 ,  H01L29/8611 ,  H01L29/8618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A diode structure fabrication method. In a P− substrate, an N+ layer is implanted. The N+ layer has an opening whose size affects the breakdown voltage of the diode structure. Upon the N+ layer, an N− layer is formed. Then, a P+ region is formed to serve as an anode of the diode structure. An N+ region can be formed on the surface of the substrate to serve as a cathode of the diode structure. By changing the size of the opening in the N+ layer during fabrication, the breakdown voltage of the diode structure can be changed (tuned) to a desired value.

Abstract translation: 二极管结构制造方法。 在P-衬底中，植入N +层。 N +层的开口尺寸影响二极管结构的击穿电压。 在N +层上形成N-层。 然后，形成P +区域作为二极管结构的阳极。 可以在衬底的表面上形成N +区以用作二极管结构的阴极。 通过在制造期间改变N +层中的开口的尺寸，可以将二极管结构的击穿电压改变（调谐）至期望的值。

公开(公告)号：US07698678B2

公开(公告)日：2010-04-13

申请号：US11837945

申请日：2007-08-13

Applicant: Steven H. Voldman

Inventor： Steven H. Voldman

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F17/5063 ,  H01G4/002

Abstract: Apparatus and program product for designing vertical parallel plate (VPP) capacitor structures in which the capacitor plates in different conductive layers of the capacitor stack have a different physical spacing. The methodology optimizes the physical spacing of the plates in each conductive layer to achieve a targeted electrostatic discharge protection level and, thereby, supply electrostatic discharge robustness.

Abstract translation: 用于设计垂直平行板（VPP）电容器结构的装置和程序产品，其中电容器堆叠的不同导电层中的电容器板具有不同的物理间隔。 该方法优化了每个导电层中板的物理间距，以达到目标静电放电保护水平，从而提供静电放电鲁棒性。

公开(公告)号：US07696541B2

公开(公告)日：2010-04-13

申请号：US12043212

申请日：2008-03-06

Applicant: Phillip Francis Chapman ,  David S. Collins ,  Steven H. Voldman

Inventor： Phillip Francis Chapman ,  David S. Collins ,  Steven H. Voldman

IPC: H01L31/112

CPC classification number: H01L27/11807 ,  H01L27/0207

Abstract: A structure, method and a design structure for preventing latchup in a gate array. The design structure including: a NFET gate array and a PFET gate array in a substrate; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate the NFET gate array and PFET gate array, the through via electrically contacting the P-well.

Abstract translation: 一种用于防止门阵列闭锁的结构，方法和设计结构。 该设计结构包括：衬底中的NFET栅极阵列和PFET门阵列; 从衬底的底表面朝向衬底的顶表面延伸的导电通孔，NFET栅极阵列和PFET门阵列，通孔电接触P阱。