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公开(公告)号：US12009791B2
公开(公告)日：2024-06-11
申请号：US17702312
申请日：2022-03-23
申请人： Analog Devices, Inc.
CPC分类号： H03F3/2175 , H03M3/412 , H03M3/464 , H04R3/02 , H03F2200/03 , H03F2200/331 , H03F2200/351
摘要： Systems and methods are provided for architectures for a digital class D driver that increase the power efficiency of the class D driver. In particular, systems and methods are provided for a digital class D driver having a feedback analog-to-digital converter (ADC) that can have a latency of 1 cycle or more than 1 cycle. A feedback ADC with a latency of 1 cycle or more is significantly lower power than a low latency feedback ADC. Systems and methods are disclosed for a power efficient digital class D driver architecture that allows for a latency of one or more cycles in the feedback ADC.
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公开(公告)号：US09800260B1
公开(公告)日：2017-10-24
申请号：US15343674
申请日：2016-11-04
发明人： Debopam Banerjee
CPC分类号： H03M3/412 , H03M1/124 , H03M3/452 , H03M3/454 , H03M3/458 , H03M3/488 , H04B1/0017 , H04B1/38
摘要： An apparatus comprises a delta-sigma analog-to-digital converter (ADC) and baseband processing circuitry. The delta-sigma ADC includes a plurality of integrator stages connected in series, including a first integrator stage operatively coupled to an input of the delta-sigma ADC; a main quantizer circuit including a main ADC circuit and a main digital-to-analog converter (DAC) circuit, wherein an input to the main ADC circuit is operatively coupled to the plurality of integrator stages; and a first feedback circuit path operatively coupled from an output of the first integrator stage to the input of the delta-sigma ADC, wherein the first feedback circuit path is configured to subtract an output voltage of the first integrator stage from the input of the delta-sigma ADC. The baseband circuitry is configured to activate the first feedback circuit path when detecting that the input voltage increases to cause distortion in the delta-sigma ADC.
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公开(公告)号：US20160087824A1
公开(公告)日：2016-03-24
申请号：US14544841
申请日：2015-02-24
发明人： Kofi A. A. Makinwa , Rui Quan
IPC分类号： H04L27/233 , H04L7/00
CPC分类号： H04L27/2334 , G01F1/66 , H03L1/022 , H03L7/00 , H03L7/0814 , H03L7/085 , H03M3/412 , H03M3/464 , H03M3/496
摘要： A phase-domain delta-sigma (ΔΣ) modulator in a phase digitizer determines a demodulated phase error based on a phase-modulated frequency signal, in which a carrier frequency is modulated with a fundamental frequency and an associated phase, and a selected one of a set of reference signals, where the demodulated phase error represents a difference between the phase and a reference phase of the selected one of the set of reference signals. Moreover, a digital filter in the phase-domain ΔΣ modulator filters the demodulated phase error. Furthermore, a latch in the phase-domain ΔΣ modulator provides a bit stream by sampling one or more bits of the filtered demodulated phase error, where an average value of the bit stream represents the phase. Next, control logic in the phase-domain ΔΣ modulator selects the one of the set of reference signals.
摘要翻译： 相位数字化仪中的相位Δ-Σ（＆Dgr＆amp; Sgr）调制器基于相位调制频率信号确定解调的相位误差，其中以基频和相关相位对载波频率进行调制， 所选择的一组参考信号中的一个，其中解调的相位误差表示所述一组参考信号中的所选择的一个的相位和参考相位之间的差。 此外，相域中的数字滤波器＆Dgr; 调制器滤波解调的相位误差。 此外，相域中的锁存器＆Dgr; 调制器通过采样滤波的解调相位误差的一个或多个比特来提供比特流，其中比特流的平均值代表相位。 接下来，相域中的控制逻辑＆Dgr＆ 调制器选择该组参考信号中的一个。
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公开(公告)号：US20130214952A1
公开(公告)日：2013-08-22
申请号：US13815225
申请日：2013-02-11
摘要： An analog-to-digital converter (ADC) is described. This ADC converts an analog signal into a digital value using a two-pass digitization process. In a first operation, coarse digitization is performed by an averaging converter based on a set of references. Then, in a second operation, fine digitization is performed by either another averaging converter or the same averaging converter based on a subset of the set of references that is progressively closer to an instantaneous value of the analog signal. For example, the coarse digitization may be performed by a low-resolution ADC stage and the fine digitization may be performed by a sigma-delta ADC, such as a single-bit sigma-delta ADC. Moreover, the other averaging converter may use dynamic element matching to shuffle reference elements used to generate the subset. In this way, the ADC may provide high resolution with reduced nonlinearity and quantization noise.
摘要翻译： 描述了一种模拟 - 数字转换器（ADC）。 该ADC使用二次数字化处理将模拟信号转换为数字值。 在第一操作中，基于一组参考的平均转换器执行粗略数字化。 然后，在第二操作中，基于逐渐接近模拟信号的瞬时值的参考集合的子集，由另一个平均转换器或相同的平均转换器执行精细数字化。 例如，粗略数字化可以由低分辨率ADC级执行，精细数字化可以由诸如单位Σ-ΔADC之类的Σ-ΔADC来执行。 此外，另一个平均转换器可以使用动态元素匹配来混洗用于生成子集的参考元素。 以这种方式，ADC可以提供具有降低的非线性和量化噪声的高分辨率。
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公开(公告)号：US07453382B2
公开(公告)日：2008-11-18
申请号：US11651925
申请日：2007-01-10
IPC分类号： H03M3/00
摘要： A method and an apparatus for converting an analog input signal into a digital output signal using a sigma-delta modulator architecture with a digital tracking filter. The digital tracking filter may have and order greater than one, and the signal and noise transfer functions of the sigma-delta modulator architecture are chosen to provide a sigma-delta modulator architecture with a high dynamic range even if a relatively low oversampling ratio is used.
摘要翻译： 一种使用具有数字跟踪滤波器的Σ-Δ调制器架构将模拟输入信号转换为数字输出信号的方法和装置。 数字跟踪滤波器可以具有大于1的数量跟踪滤波器，并且选择Σ-Δ调制器架构的信号和噪声传递函数以提供具有高动态范围的Σ-Δ调制器架构，即使使用相对较低的过采样比 。
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公开(公告)号：US07084800B2
公开(公告)日：2006-08-01
申请号：US10767774
申请日：2004-01-30
申请人： Kevin Lee Miller
发明人： Kevin Lee Miller
IPC分类号： H03M1/66
摘要： A sequence mapping circuit and method for digital audio circuits generates a pulsed output. Over time, the mapping circuit generates pulses with a substantially identical average centroid for each of the possible output waveforms. For at least some of the output waveforms, two or more sets of pulses are provided representing the same waveform but having different centroids. The output is alternated among the available sets of pulses to maintain the desired average centroid over time. Shuffling of the output among the available pulses representing a given waveform may be randomly determined, or the pulses used may be tracked and the output pulses sequentially alternated among the available output pulses. The shuffled mapping method reduces output harmonics compared to conventional static mappers.
摘要翻译： 用于数字音频电路的序列映射电路和方法产生脉冲输出。 随着时间的推移，映射电路为每个可能的输出波形产生具有基本相同的平均质心的脉冲。 对于至少一些输出波形，提供表示相同波形但具有不同质心的两组或多组脉冲。 输出在可用的脉冲组之间交替，以保持期望的平均质心。 表示给定波形的可用脉冲之间的输出的混洗可以是随机确定的，或者可以跟踪使用的脉冲，并且输出脉冲在可用输出脉冲之间顺序交替。 与传统静态映射器相比，混洗映射方法降低了输出谐波。
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公开(公告)号：US07038607B2
公开(公告)日：2006-05-02
申请号：US10767775
申请日：2004-01-30
申请人： Kevin Lee Miller
发明人： Kevin Lee Miller
IPC分类号： H03M1/66
摘要： A modulator circuit receives a modulator input signal and produces a mapper output signal. The modulator circuit includes a filter circuit that generates an output that is a function of the modulator input signal and of the mapper output signal. A quantizer receives the filter output signal and produces a quantized representation of the filter output signal. A mapper receives the quantizer output and generates the mapper output signal.
摘要翻译： 调制器电路接收调制器输入信号并产生映射器输出信号。 调制器电路包括产生作为调制器输入信号和映射器输出信号的函数的输出的滤波器电路。 量化器接收滤波器输出信号并产生滤波器输出信号的量化表示。 映射器接收量化器输出并产生映射器输出信号。
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公开(公告)号：US20040189500A1
公开(公告)日：2004-09-30
申请号：US10480266
申请日：2003-12-08
发明人： Engel Roza
IPC分类号： H03M003/00
摘要： A pipeline AD converter comprising a cascade of AD-converter stages, whereby the sampling noise generated by a former stage of the cascade is AD-converted by the next stage in the cascade and the digital signals of the stages are combined to generate an error-reduced digital representation of the analog input signal. Applying the input signal to a synchronous nullnull modulator and to an asynchronous nullnull modulator and comparing the output signals of the nullnull modulators generates the sampling noise.
摘要翻译： 一种流水线AD转换器，其包括级联的AD转换器级，由此级联的前级产生的采样噪声由级联中的下一级进行AD转换，并且级的数字信号被组合以产生误差 - 降低模拟输入信号的数字表示。 将输入信号应用于同步SigmaDelta调制器和异步SigmaDelta调制器，并比较SigmaDelta调制器的输出信号会产生采样噪声。
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公开(公告)号：US20190245553A1
公开(公告)日：2019-08-08
申请号：US15935045
申请日：2018-03-25
申请人： NXP B.V.
IPC分类号： H03M3/00
摘要： A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal; a first summing junction configured to subtract a feedback analog signal from the input analog signal; a loop filter configured to filter an output signal from the first summing junction (304): an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC comprises a plurality of N-bit comparator latches that are each locally time-interleaved with at least a pair of latches and configured to function in a complementary manner and provide a combined complementary output.
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