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公开(公告)号：US20160352557A1
公开(公告)日：2016-12-01
申请号：US14723171
申请日：2015-05-27
Applicant: Xilinx, Inc.
Inventor： Yu Liao , Geoffrey Zhang , Hongtao Zhang , Kun-Yung Chang , Toan Pham , Zhaoyin D. Wu
CPC classification number: H04L27/3809 , H04L25/03057 , H04L25/03885
Abstract: A receiver relates generally to channel adaptation. In this receiver, a first signal processing block is coupled to a communications channel. The first signal processing block includes: an AGC block and a CTLE block for receiving a modulated signal for providing an analog signal; an ADC for converting the analog signal to digital samples; and an FFE block for equalizing the digital samples to provide equalized samples. A second signal processing block includes: a DFE block for receiving the equalized sampled for providing re-equalized samples; and a slicer coupled to the DFE block for slicing the re-equalized samples. A receiver adaptation block is coupled to the first signal processing block and the second signal processing block. The receiver adaptation block is configured for providing an AGC adaptation, a CTLE adaptation, and a slicer adaptation to the communications channel.
Abstract translation: 接收机一般涉及信道适配。 在该接收机中，第一信号处理块耦合到通信信道。 第一信号处理块包括：AGC块和CTLE块，用于接收用于提供模拟信号的调制信号; 用于将模拟信号转换为数字样本的ADC; 以及用于均衡数字样本以提供均衡样本的FFE块。 第二信号处理块包括：DFE块，用于接收用于提供重新均衡的采样的采样的均衡; 以及耦合到DFE块的限幅器，用于对重新平衡的样本进行切片。 接收机适配块耦合到第一信号处理块和第二信号处理块。 接收器适配块被配置用于提供AGC适配，CTLE适配和对通信信道的限幅器适配。
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公开(公告)号：US09654327B2
公开(公告)日：2017-05-16
申请号：US14723171
申请日：2015-05-27
Applicant: Xilinx, Inc.
Inventor： Yu Liao , Geoffrey Zhang , Hongtao Zhang , Kun-Yung Chang , Toan Pham , Zhaoyin D. Wu
CPC classification number: H04L27/3809 , H04L25/03057 , H04L25/03885
Abstract: A receiver relates generally to channel adaptation. In this receiver, a first signal processing block is coupled to a communications channel. The first signal processing block includes: an AGC block and a CTLE block for receiving a modulated signal for providing an analog signal; an ADC for converting the analog signal to digital samples; and an FFE block for equalizing the digital samples to provide equalized samples. A second signal processing block includes: a DFE block for receiving the equalized sampled for providing re-equalized samples; and a slicer coupled to the DFE block for slicing the re-equalized samples. A receiver adaptation block is coupled to the first signal processing block and the second signal processing block. The receiver adaptation block is configured for providing an AGC adaptation, a CTLE adaptation, and a slicer adaptation to the communications channel.
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公开(公告)号：US09379720B1
公开(公告)日：2016-06-28
申请号：US14715280
申请日：2015-05-18
Applicant: Xilinx, Inc.
Inventor： Yu Xu , Santiago G. Asuncion , Tianqi Tang , Toan Pham , Kun-Yung Chang
CPC classification number: H04L7/0337
Abstract: Clock data recovery can be accomplished using a phase path circuit that is configured to receive a data signal and a clock signal. A phase detection circuit detects phase differences between the data signal and a plurality of clock signals and generates a phase adjustment signal based upon a majority voting of the detected phase differences. Speculative calculation circuits generate speculative phase selection signals. Selection circuits select, in response to the phase adjustment signal, from speculative phase selection signals to provide outputs of the phase path circuit.
Abstract translation: 可以使用被配置为接收数据信号和时钟信号的相位路径电路来实现时钟数据恢复。 相位检测电路检测数据信号和多个时钟信号之间的相位差，并且基于检测到的相位差的多数投票产生相位调整信号。 投机计算电路产生推测相位选择信号。 选择电路响应于相位调整信号从推测相位选择信号中选择以提供相位路径电路的输出。
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