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    Unified container for hardware and software binaries
    1.
    发明授权
    Unified container for hardware and software binaries 有权

    公开(公告)号：US11720422B1

    公开(公告)日：2023-08-08

    申请号：US17198887

    申请日：2021-03-11

    Applicant: Xilinx, Inc.

    Inventor： Hem C. Neema ,  Sonal Santan ,  Soren T. Soe ,  Stephen P. Rozum ,  Nik Cimino

    IPC: G06F9/54 ,  G06F21/53 ,  G06F8/41 ,  G06F21/57 ,  G06F8/65

    CPC classification number: G06F9/545 ,  G06F8/44 ,  G06F21/53 ,  G06F21/572 ,  G06F8/65

    Abstract: A unified container file can be selected using computer hardware. The unified container file can include a plurality of files embedded therein used to configure a programmable integrated circuit (IC). The plurality of files can include a first partial configuration bitstream and a second partial configuration bitstream. The unified container file also includes metadata specifying a defined relationship between the first partial configuration bitstream and the second partial configuration bitstream for programming the programmable IC. The defined relationship can be determined using computer hardware by reading the metadata from the unified container file. The programmable IC can be configured, using the computer hardware, based on the defined relationship specified by the metadata using the first partial configuration bitstream and the second partial configuration bitstream.

    TRANSPARENT AND REMOTE KERNEL EXECUTION IN A HETEROGENEOUS COMPUTING SYSTEM
    2.
    发明公开
    TRANSPARENT AND REMOTE KERNEL EXECUTION IN A HETEROGENEOUS COMPUTING SYSTEM 审中-公开

    公开(公告)号：US20230229497A1

    公开(公告)日：2023-07-20

    申请号：US17648172

    申请日：2022-01-17

    Applicant: Xilinx, Inc.

    Inventor： Sonal Santan ,  Yu Liu ,  Yenpang Lin ,  Stephen P. Rozum

    IPC: G06F9/50 ,  G06F9/54 ,  G06F9/30 ,  G06F12/02

    CPC classification number: G06F9/5016 ,  G06F9/544 ,  G06F9/30043 ,  G06F12/0238 ,  G06F2212/7201

    Abstract: Remote kernel execution in a heterogeneous computing system can include executing, using a device processor of a device communicatively linked to a host processor, a device runtime and receiving from the host processor within a hardware submission queue of the device, a command. The command requests execution of a software kernel and specifies a descriptor stored in a region of a memory of the device shared with the host processor. In response to receiving the command, the device runtime, as executed by the device processor, invokes a runner program associated with the software kernel. The runner program can map a physical address of the descriptor to a virtual memory address corresponding to the descriptor that is usable by the software kernel. The runner program can execute the software kernel. The software kernel can access data specified by the descriptor using the virtual memory address as provided by the runner program.

    Transparent and remote kernel execution in a heterogeneous computing system
    3.
    发明授权
    Transparent and remote kernel execution in a heterogeneous computing system 有权

    公开(公告)号：US12204940B2

    公开(公告)日：2025-01-21

    申请号：US17648172

    申请日：2022-01-17

    Applicant: Xilinx, Inc.

    Inventor： Sonal Santan ,  Yu Liu ,  Yenpang Lin ,  Stephen P. Rozum

    IPC: G06F9/50 ,  G06F9/30 ,  G06F9/54 ,  G06F12/02

    Abstract: Remote kernel execution in a heterogeneous computing system can include executing, using a device processor of a device communicatively linked to a host processor, a device runtime and receiving from the host processor within a hardware submission queue of the device, a command. The command requests execution of a software kernel and specifies a descriptor stored in a region of a memory of the device shared with the host processor. In response to receiving the command, the device runtime, as executed by the device processor, invokes a runner program associated with the software kernel. The runner program can map a physical address of the descriptor to a virtual memory address corresponding to the descriptor that is usable by the software kernel. The runner program can execute the software kernel. The software kernel can access data specified by the descriptor using the virtual memory address as provided by the runner program.

    Method and apparatus for unified out-of-context flow and automation for IP reuse and hierarchical design flows
    5.
    发明授权
    Method and apparatus for unified out-of-context flow and automation for IP reuse and hierarchical design flows 有权
    用于IP重用和层次化设计流程的统一的上下文流和自动化的方法和装置

    公开(公告)号：US08839166B1

    公开(公告)日：2014-09-16

    申请号：US13837234

    申请日：2013-03-15

    Applicant: Xilinx, Inc.

    Inventor： Sudipto Chakraborty ,  David A. Knol ,  Stephen P. Rozum ,  Ryan A. Linderman ,  Derrick S. Woods

    IPC: G06F17/50

    CPC classification number: G06F17/5054 ,  G06F17/505 ,  G06F2217/66

    Abstract: A method, non-transitory computer readable medium and apparatus for using an out-of-context sub-block in a hierarchical design flow for an integrated circuit are disclosed. For example, the method identifies one or more sub-blocks in the hierarchical design flow that are eligible for creating the out-of-context sub-block, receives a selection of one of the one or more sub-blocks that are eligible and creates the out-of-context sub-block for the one of the one or more sub-blocks that is selected.

    Abstract translation: 公开了一种用于在集成电路的分层设计流程中使用失去上下文子块的方法，非暂时计算机可读介质和装置。 例如，该方法识别分层设计流程中的一个或多个子块，该子块有资格创建失去上下文的子块，接收一个或多个符合条件并创建的子块中的一个的选择 用于所选择的一个或多个子块中的一个的上下文子块。

    Unified container for hardware and software binaries
    6.
    发明授权
    Unified container for hardware and software binaries 有权

    公开(公告)号：US10956241B1

    公开(公告)日：2021-03-23

    申请号：US15848691

    申请日：2017-12-20

    Applicant: Xilinx, Inc.

    Inventor： Hem C. Neema ,  Sonal Santan ,  Soren T. Soe ,  Stephen P. Rozum ,  Nik Cimino

    IPC: G06F8/41 ,  G06F9/54 ,  G06F21/57 ,  G06F21/53 ,  G06F8/65

    Abstract: A computer program product can include a non-transitory computer readable storage medium storing a unified container. The unified container can include a header structure, wherein the header structure has a fixed length and specifies a number of section headers included in the unified container. The unified container can include a plurality of section headers equivalent to the number of section headers specified in the header structure. The unified container can include a plurality of data sections corresponding to the plurality of section headers on a one-to-one basis. The plurality of data sections includes a first data section including a hardware binary and a second data section including a software binary. The hardware binary and the software binary are configured to program a programmable integrated circuit. Each section header specifies a type of data stored in the corresponding data section and specifies a mapping for the corresponding data section.

    Updating block random access memory contents using memory emulation
    7.
    发明授权
    Updating block random access memory contents using memory emulation 有权

    公开(公告)号：US10303385B1

    公开(公告)日：2019-05-28

    申请号：US15451967

    申请日：2017-03-07

    Applicant: Xilinx, Inc.

    Inventor： Michael Keilson ,  Stephen P. Rozum ,  Ryan A. Linderman ,  Pradip Kar

    IPC: G06F3/06 ,  G06F17/50 ,  G11C8/16

    Abstract: Modifying initialization data for a memory array of a circuit design can include providing, using a processor, portions of an incoming stream of data for initializing the memory array to emulation objects of a memory array emulator. The memory array emulator is configured to emulate an implementation of the memory array and the emulation objects represent block random access memories (block RAMs) of the memory array. Using the processor, the data can be formatted using the emulation objects to generate initialization data, wherein the data is formatted based upon configuration settings of the block RAMs emulated by the respective emulation objects. A configuration bitstream can be updated, using the processor, with the initialization data.

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