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    Multi-chip stacked devices
    2.
    发明授权
    Multi-chip stacked devices 有权

    公开(公告)号：US11127718B2

    公开(公告)日：2021-09-21

    申请号：US16741319

    申请日：2020-01-13

    Applicant: XILINX, INC.

    Inventor： Anil Kumar Kandala ,  Vijay Kumar Koganti ,  Santosh Yachareni

    IPC: H01L21/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/528 ,  H01L23/00 ,  H01L25/00

    Abstract: Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack that includes chips. One or more chips each includes a selection circuit and a broken via pillar that includes first and second continuous portions. The first continuous portion includes a through substrate via and a first metal line. The second continuous portion includes a second metal line. The first and second metal lines are disposed within dielectric layers disposed on a side of the semiconductor substrate of the respective chip. The first and second continuous portions are aligned in a direction normal to the side of the semiconductor substrate. An input node of the selection circuit is connected to one of the first or second metal line. An output node of the selection circuit is connected to the other of the first or second metal line.

    Multi-chip stacked devices
    5.
    发明授权
    Multi-chip stacked devices 有权

    公开(公告)号：US11004833B1

    公开(公告)日：2021-05-11

    申请号：US16792560

    申请日：2020-02-17

    Applicant: XILINX, INC.

    Inventor： Anil Kumar Kandala ,  Vijay Kumar Koganti ,  Santosh Yachareni ,  Sundeep Ram Gopal Agarwal

    IPC: H01L25/065 ,  H01L23/48

    Abstract: Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack that includes chips. Neighboring chips are connected to each other. Plural chips of the chips collectively include columns of broken via pillars and bridges. Each of the plural chips has a broken via pillar in each column. The broken via pillar has first and second continuous via pillar portions aligned in a direction normal to a side of a semiconductor substrate of the respective chip. The first continuous via pillar portion is not connected within the broken via pillar to the second continuous via pillar portion. Each of the plural chips has one or more of the bridges. Each bridge connects, within the respective chip, the first continuous via pillar portion in a column and the second continuous via pillar portion in another column.

    Multi-chip stacked devices
    7.
    发明授权
    Multi-chip stacked devices 有权

    公开(公告)号：US10886921B1

    公开(公告)日：2021-01-05

    申请号：US16825340

    申请日：2020-03-20

    Applicant: XILINX, INC.

    Inventor： Vijay Kumar Koganti ,  Anil Kumar Kandala ,  Santosh Yachareni

    IPC: G06F7/38 ,  H03K19/177 ,  H03K19/173 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H03K19/20

    Abstract: Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack including a base chip and two or more overlying chips overlying the base chip. Neighboring chips of the chip stack are connected to each other. The chip stack includes identification generation connections and circuits configured to generate a unique identification of each overlying chip based on a relative position of the respective overlying chip with reference to the base chip. The chip stack includes a communication channel from the base chip to each overlying chip. Each overlying chip includes comparison and enable/disable logic (CEDL) communicatively coupled to the communication channel. The CEDL is configured to compare a target identification of data received by the respective overlying chip to the unique identification of the respective overlying chip and responsively enable or disable a recipient circuit of the respective overlying chip.

    Glitch detector and test glitch generator
    8.
    发明授权
    Glitch detector and test glitch generator 有权

    公开(公告)号：US10466275B1

    公开(公告)日：2019-11-05

    申请号：US16022403

    申请日：2018-06-28

    Applicant: Xilinx, Inc.

    Inventor： Sandeep Vundavalli ,  Sree RKC Saraswatula ,  James D. Wesselkamper ,  Santosh Yachareni ,  Shidong Zhou ,  Anil Kumar Kandala

    IPC: G11C29/00 ,  G01R11/24 ,  G01R31/30 ,  G06F21/86 ,  G06F21/76 ,  G01R22/06

    Abstract: Apparatus and associated methods relate to a glitch detection circuit monitoring a duration that a selected fractional supply voltage is below a predetermined voltage threshold. The selected fractional supply voltage may be at the predetermined threshold when the supply voltage is between a valid circuit-supply voltage and a power-on circuit-reset (POR). A glitch detect signal may be generated, for example, when the monitored duration is greater than a predetermined duration threshold. A test glitch generator may generate a test glitch, for example, having selectable voltage and duration, which may be selectably applied to the glitch detection circuit to verify operation. Various exemplary glitch detection circuits may advantageously determine externally produced tampering attempts by detecting circuit-supply voltages and durations that meet specific selectable supply voltage and duration criteria, improving security of sensitive field programmable gate array (FPGA) data by taking protective action in response to the detection.

    Current-encoded signaling
    10.
    发明授权
    Current-encoded signaling 有权
    电流编码信令

    公开(公告)号：US09166584B1

    公开(公告)日：2015-10-20

    申请号：US14300146

    申请日：2014-06-09

    Applicant: Xilinx, Inc.

    Inventor： Anil Kumar Kandala ,  Srinivasa L. Karumajji ,  Vikram Santurkar

    IPC: H03K19/173 ,  H03K19/00 ,  H03K19/0175

    CPC classification number: H03K19/0013 ,  H03K19/017509 ,  H03K19/017581

    Abstract: An apparatus is disclosed for communication of data signals in a current-encoded format. The apparatus includes a first logic block and a second logic block. The first logic block includes a first voltage-mode logic (VML) circuit configured to provide a first voltage-encoded binary signal and an encoder circuit configured to convert the voltage-encoded binary signal to a current-encoded binary signal. The second logic block includes a decoder circuit configured to receive the current-encoded binary signal from the first logic block and convert the current-encoded binary signal to a second voltage-encoded binary signal. The logic states encoded by the second voltage-encoded binary signal are equal to the logic states encoded by the first voltage-encoded binary signal. The second logic block also includes a second VML circuit coupled to the decoder circuit and configured to receive and process the second voltage-encoded binary signal.

    Abstract translation: 公开了一种用于以当前编码格式通信数据信号的装置。 该装置包括第一逻辑块和第二逻辑块。 第一逻辑块包括被配置为提供第一电压编码二进制信号的第一电压模式逻辑（VML）电路和被配置为将电压编码二进制信号转换为电流编码二进制信号的编码器电路。 第二逻辑块包括被配置为从第一逻辑块接收当前编码的二进制信号并将当前编码的二进制信号转换为第二电压编码二进制信号的解码器电路。 由第二电压编码二进制信号编码的逻辑状态等于由第一电压编码二进制信号编码的逻辑状态。 第二逻辑块还包括耦合到解码器电路并被配置为接收和处理第二电压编码二进制信号的第二VML电路。

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