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公开(公告)号：US12072594B2
公开(公告)日：2024-08-27
申请号：US17607852
申请日：2021-09-08
Inventor： Zhilin Wu , Tao Ma , Dewei Song , Fei Ai
IPC: G02F1/1368 , G02F1/1333 , G02F1/1343 , G02F1/1362
CPC classification number: G02F1/136295 , G02F1/13338 , G02F1/1343 , G02F1/136209 , G02F1/136227 , G02F1/1368
Abstract: The present application discloses a display panel and an electrical terminal. The display panel includes: an underlay; an array driver layer located on the underlay and including a gate electrode layer and a source and drain electrode layer; a signal line including an adaptor portion located in the non-display region, wherein the adaptor portion includes a first wire section disposed in a same layer with the gate electrode layer, a second wire section disposed in a same layer with the source and drain electrode layer, and a bridge portion electrically connected to the first wire section and the second wire section; wherein the first wire section, the second wire section, and the bridge portion are disposed in different layers.
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公开(公告)号：US20240222379A1
公开(公告)日：2024-07-04
申请号：US17998999
申请日：2022-11-07
Inventor： Zhifu LI , Guanghui LIU , Fei Al , Dewei Song
IPC: H01L27/12
CPC classification number: H01L27/1222
Abstract: Embodiments of the present disclosure provide an array substrate and a display panel. The array substrate includes a first active layer, a gate electrode, a gate insulating layer, a second active layer, and a source/drain metal layer. The first active layer is connected in parallel with the second active layer through a conductor layer. Through an active layer structure with two layers in parallel, an on-state current and mobility of equivalent carriers of a device are effectively improved, and a comprehensive performance of the device is improved.
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公开(公告)号：US20210041733A1
公开(公告)日：2021-02-11
申请号：US16613419
申请日：2019-10-18
Inventor： Fei AI , Dewei Song
IPC: G02F1/1333 , G02F1/1362 , G02F1/1343 , G02F1/1368 , G06F3/041
Abstract: An array substrate, a method of manufacturing the same and a touch display panel are disclosed. An inorganic insulating layer, a plurality of common electrodes and a passivation layer are sequentially manufactured on a substrate formed with a plurality of thin film transistors and a plurality of touch signal lines. The passivation layer and the inorganic insulating layer are patterned to form a plurality of first via holes exposing drain electrodes of the thin film transistors and the touch signal lines, and to form a plurality of second via holes exposing the common electrodes in such a manner that the touch signal lines and the common electrodes are bridged through the touch electrodes formed on a surface of the passivation layer.
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公开(公告)号：US12164195B2
公开(公告)日：2024-12-10
申请号：US17925028
申请日：2022-11-08
Inventor： Fei Ai , Dewei Song , Chengzhi Luo
IPC: G02F1/1335 , G02F1/1333 , G02F1/1368
Abstract: A display panel and a manufacturing method thereof, and a display device are provided. The display panel includes a backlight module and an array substrate. The array substrate includes an insulation structure is located in the opening region. A first groove is defined at a side of the insulation structure away from the backlight module. A first insulation layer and a second insulation layer are filled in the first groove. The second insulation layer is located on a side of the first insulation layer close to the backlight module, and a refractive index of the second insulation layer is less than a refractive index of the first insulation layer.
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公开(公告)号：US12087782B2
公开(公告)日：2024-09-10
申请号：US17260982
申请日：2020-11-24
Inventor： Fei Ai , Jiyue Song , Dewei Song
IPC: H01L27/146 , G02F1/1343 , G02F1/1362 , G02F1/1368 , G06F3/041 , G06V40/13
CPC classification number: H01L27/14603 , G02F1/13439 , G02F1/136227 , H01L27/14692 , G02F1/134363 , G02F1/13685 , G06F3/0412 , G06V40/1318 , H01L27/14612 , H01L27/14643
Abstract: An array substrate, a display panel, and an electronic device are provided. The array substrate includes a substrate, a first conductive layer including a first connection part, a fourth insulating layer disposed on the first conductive layer and provided with a second via, and a second conductive layer disposed on the fourth insulating layer and in the second via. The second conductive layer includes a second electrode, and the second electrode is connected to the first connection part through the second via.
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Patent Agency Ranking
公开(公告)号：US12033424B2
公开(公告)日：2024-07-09
申请号：US17052110
申请日：2020-08-14
Inventor： Jianfeng Yuan , Fan Gong , Fei Ai , Jiyue Song , Dewei Song , Shiyu Long
IPC: G06V40/13 , G02F1/1333 , G02F1/1335 , G02F1/1339 , G02F1/1343 , G02F1/1362 , G02F1/1368 , G06F3/041 , G06F3/044 , H01L31/0376 , H01L31/113
CPC classification number: G06V40/1318 , G02F1/13338 , G02F1/133514 , G02F1/1339 , G02F1/134309 , G02F1/136286 , G02F1/1368 , G06F3/0412 , G06F3/0445 , H01L31/03762 , H01L31/1136
Abstract: A light-sensitive sensor, an array substrate, and an electronic equipment are provided. The light-sensitive sensor includes a third metal layer, a second semiconductor layer, and a fourth metal layer. The third metal layer includes a second gate. The second semiconductor layer includes conductive portions, and the conductive portions are disposed at both ends of the second semiconductor layer. The fourth metal layer disposed on the second semiconductor layer, and the fourth metal layer includes a second source and a second drain.
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公开(公告)号：US11847850B2
公开(公告)日：2023-12-19
申请号：US17598517
申请日：2021-07-01
Inventor： Dewei Song , Fei Ai , Jiyue Song
CPC classification number: G06V40/1306 , G06V40/1318 , H01L27/127 , H01L27/1222 , H01L27/1288
Abstract: An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes a substrate, a metal electrode layer, a first passivation layer, a first electrode layer, a photosensitive semiconductor layer, a second passivation layer, and a second electrode layer. The first electrode layer and the photosensitive semiconductor layer are both disposed on a surface of the first passivation layer away from the metal electrode layer.
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公开(公告)号：US11835808B2
公开(公告)日：2023-12-05
申请号：US17051929
申请日：2020-08-05
Inventor： Fei Ai , Jiyue Song , Dewei Song
IPC: G02F1/1333 , G02F1/1343 , G02F1/1368
CPC classification number: G02F1/13338 , G02F1/1343 , G02F1/1368
Abstract: The embodiment of the present application discloses an array substrate, a display panel, and an electronic device. The array substrate includes a substrate and includes a control element; a first electrode is connected to the control element; a PIN diode is arranged on the first electrode, The PIN diode covers at least a part of the semiconductor layer of the control element and a part of the first electrode; a second conductive layer is arranged on the PIN diode, and the second conductive layer includes a second electrode.
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公开(公告)号：US11862642B2
公开(公告)日：2024-01-02
申请号：US16966119
申请日：2020-04-20
Inventor： Juncheng Xiao , Yong Xu , Fei Ai , Dewei Song
CPC classification number: H01L27/1225 , H01L27/1285 , H01L27/1288
Abstract: A display panel, an array substrate, and a manufacturing method thereof, wherein the array substrate includes a thin film transistor device, and an interface layer, a first transparent conductive layer, a passivation layer, and a second transparent conductive layer which are formed on the thin film transistor device in sequence. By replacing a planarization layer in the prior art with the interface layer, performing a gate re-etching process, and perforating the interface layer and the passivation layer to simultaneously form a deep via and a shallow via, a number of photomasks required to form the array substrate is reduced to 8. It effectively reduces costs of production materials and costs of photomasks.
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公开(公告)号：US20230094760A1
公开(公告)日：2023-03-30
申请号：US17051929
申请日：2020-08-05
Inventor： Fei Ai , Jiyue Song , Dewei Song
IPC: G02F1/1333 , G02F1/1368 , G02F1/1343
Abstract: The embodiment of the present application discloses an array substrate, a display panel, and an electronic device. The array substrate includes a substrate and includes a control element; a first electrode is connected to the control element; a PIN diode is arranged on the first electrode, The PIN diode covers at least a part of the semiconductor layer of the control element and a part of the first electrode; a second conductive layer is arranged on the PIN diode, and the second conductive layer includes a second electrode.
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