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公开(公告)号：US10553575B2
公开(公告)日：2020-02-04
申请号：US15815289
申请日：2017-11-16
Inventor： Li-Chun Tien , Ya-Chi Chou , Hui-Zhong Zhuang , Chun-Fu Chen , Ting-Wei Chiang , Hsiang Jen Tseng
IPC: H01L27/02 , H01L27/118 , G06F17/50
Abstract: A semiconductor device includes an array of Engineering Change Order (ECO) cells. Each of the ECO cells in the array includes a first metal pattern and a second metal pattern. Each of the ECO cells in the array further includes a plurality of active area patterns isolated from each other and arranged between the first and second metal patterns. Each of the ECO cells in the array further includes a first central metal pattern overlapping the first metal pattern. Each of the ECO cells in the array further includes a via electrically connecting the first central metal pattern to the first metal pattern. The plurality of active area patterns is arranged symmetrically about the first central metal pattern.
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2.发明授权公开(公告)号：US10289789B2
公开(公告)日：2019-05-14
申请号：US15601697
申请日：2017-05-22
Inventor： Shang-Chih Hsieh , Hui-Zhong Zhuang , Ting-Wei Chiang , Chun-Fu Chen , Hsiang-Jen Tseng
IPC: G06F17/50 , H01L27/02 , H01L21/768 , H01L27/118
Abstract: An integrated circuit designing system includes a non-transitory storage medium and a hardware processor. The non-transitory storage medium is encoded with a layout of a standard cell corresponding to a predetermined manufacturing process. The predetermined manufacturing process has a nominal minimum pitch, along a predetermined direction, of metal lines. The layout of the standard cell has a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.
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公开(公告)号：US20150035070A1
公开(公告)日：2015-02-05
申请号：US13955796
申请日：2013-07-31
Inventor： Ting-Wei Chiang , Chun-Fu Chen , Hsiang-Jen Tseng , Wei-Yu Chen , Hui-Zhong Zhuang , Shang-Chih Hsieh , Li-Chun Tien
IPC: H01L27/092 , G06F17/50
CPC classification number: H01L27/092 , G06F17/5068 , H01L21/823437 , H01L27/0207 , H01L27/088
Abstract: An integrated circuit layout includes a first active region, a second active region, a first PODE (poly on OD edge), a second PODE, a first transistor and a second transistor. The first transistor, on the first active region, includes a gate electrode, a source region and a drain region. The second transistor, on the second active region, includes a gate electrode, a source region and a drain region. The first active region and the second active region are adjacent and electrically disconnected with each other. The first PODE and the second PODE are on respective adjacent edges of the first active region and the second active region. The source regions of the first and second transistor are adjacent with the first PODE and the second PODE respectively. The first PODE and the second PODE are sandwiched between source regions of the first transistor and the second transistor.
Abstract translation: 集成电路布局包括第一有源区，第二有源区，第一PODE（OD边缘上的poly），第二PODE，第一晶体管和第二晶体管。 在第一有源区上的第一晶体管包括栅电极，源极区和漏极区。 在第二有源区上的第二晶体管包括栅电极，源极区和漏极区。 第一有源区和第二有源区相邻并且彼此电断开。 第一PODE和第二PODE位于第一有源区和第二有源区的相邻相邻边缘上。 第一和第二晶体管的源极区分别与第一PODE和第二PODE相邻。 第一PODE和第二PODE夹在第一晶体管和第二晶体管的源极区之间。
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4.发明授权公开(公告)号：US09831230B2
公开(公告)日：2017-11-28
申请号：US13965648
申请日：2013-08-13
Inventor： Li-Chun Tien , Ya-Chi Chou , Hui-Zhong Zhuang , Chun-Fu Chen , Ting-Wei Chiang , Hsiang Jen Tseng
IPC: G06F17/50 , H01L27/02 , H01L27/118
CPC classification number: H01L27/0207 , G06F17/5068 , H01L27/11807 , H01L2027/11875
Abstract: A layout of a standard cell is stored on a non-transitory computer-readable medium and includes a first conductive pattern, a second conductive pattern, a plurality of active area patterns and a first central conductive pattern. The plurality of active area patterns is isolated from each other and arranged in a first row and a second row between the first and second conductive patterns. The first row is adjacent the first conductive pattern and includes a first active area pattern and a second active area pattern among the plurality of active area patterns. The second row is adjacent the second conductive pattern and includes a third active area pattern and a fourth active area pattern among the plurality of active area patterns. The first central conductive pattern is arranged between the first and second active area patterns. The first central conductive pattern overlaps the first conductive pattern.
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5.发明授权公开(公告)号：US09501600B2
公开(公告)日：2016-11-22
申请号：US14051881
申请日：2013-10-11
Inventor： Shang-Chih Hsieh , Hui-Zhong Zhuang , Ting-Wei Chiang , Chun-Fu Chen , Hsiang-Jen Tseng
CPC classification number: G06F17/5072 , G06F17/5068 , H01L27/0207 , H03K19/02
Abstract: An integrated circuit is manufactured by a predetermined manufacturing process having a nominal minimum pitch of metal lines. The integrated circuit includes a plurality of metal lines extending along a first direction and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines is separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. The plurality of standard cells includes a first standard cell configured to perform a predetermined function and having a first layout and a second standard cell configured to perform the predetermined function and having a second layout different than the first layout. The first and second standard cells have a cell height (H) along the second direction, and the cell height being a non-integral multiple of the nominal minimum pitch.
Abstract translation: 通过具有金属线的标称最小间距的预定制造工艺制造集成电路。 集成电路包括沿着第一方向延伸的多条金属线和多条金属线下的多个标准单元。 多个金属线在与第一方向垂直的第二方向上以标称最小间距的整数倍分开。 多个标准单元包括被配置为执行预定功能并具有第一布局的第一标准单元和被配置为执行预定功能并且具有与第一布局不同的第二布局的第二标准单元。 第一和第二标准单元沿着第二方向具有单元高度（H），单元高度是标称最小间距的非整数倍。
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Patent Agency Ranking
公开(公告)号：US09158877B2
公开(公告)日：2015-10-13
申请号：US14015924
申请日：2013-08-30
Inventor： Shang-Chih Hsieh , Hui-Zhong Zhuang , Ting-Wei Chiang , Chun-Fu Chen , Hsiang-Jen Tseng
CPC classification number: G06F17/5072 , G06F17/5068 , H01L21/823431 , H01L21/823821 , H01L21/845 , H01L29/785
Abstract: A semiconductor structure includes a first active area structure, an isolation structure surrounding the first active area structure, a first polysilicon structure, a first metal structure, and a second metal structure. The first polysilicon structure is over the first active area structure. The first metal structure is directly over a first portion of the first active area structure. The second metal structure is directly over and in contact with a portion of the first polysilicon structure and in contact with the first metal structure.
Abstract translation: 半导体结构包括第一有源区结构，围绕第一有源区结构的隔离结构，第一多晶硅结构，第一金属结构和第二金属结构。 第一个多晶硅结构超过了第一个有源区结构。 第一金属结构直接在第一有源区结构的第一部分之上。 第二金属结构直接与第一多晶硅结构的一部分接触并与第一金属结构接触。
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公开(公告)号：US10380306B2
公开(公告)日：2019-08-13
申请号：US15356817
申请日：2016-11-21
Inventor： Shang-Chih Hsieh , Hui-Zhong Zhuang , Ting-Wei Chiang , Chun-Fu Chen , Hsiang-Jen Tseng
Abstract: An integrated circuit designing system includes a non-transitory storage medium that is encoded with first and second sets of standard cell layouts that are configured for performing a selected function and which correspond to a specific manufacturing process. The manufacturing process is characterized by a nominal minimum pitch (T) for metal lines with each of the standard cell layouts being characterized by a cell height (H) that is a non-integral multiple of the nominal minimum pitch. The system also includes a hardware processor coupled to the storage medium for executing a set of instructions for generating an integrated circuit layout utilizing a combination of the first and second set of standard cell layouts and the nominal minimum pitch. The first and second sets of standard layouts are related in that each of the second set of standard cell layouts corresponds to a transformed version of a corresponding standard cell layout from the first set of standard cell layouts.
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公开(公告)号：US12153868B2
公开(公告)日：2024-11-26
申请号：US18064027
申请日：2022-12-09
Inventor： Shang-Chih Hsieh , Chun-Fu Chen , Ting-Wei Chiang , Hui-Zhong Zhuang , Hsiang-Jen Tseng
IPC: G06F30/392 , H01L21/768 , H01L27/02 , H01L27/118
Abstract: An integrated circuit includes a plurality of metal lines extending along a first direction, the plurality of metal lines being separated, in a second direction perpendicular to the first direction, by integral multiples of a nominal minimum pitch. The integrated circuit further includes a plurality of standard cells, at least one of the plurality of standard cells having a cell height along the second direction being a non-integral multiple of the nominal minimum pitch.
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9.发明授权公开(公告)号：US11544437B2
公开(公告)日：2023-01-03
申请号：US17109820
申请日：2020-12-02
Inventor： Shang-Chih Hsieh , Chun-Fu Chen , Ting-Wei Chiang , Hui-Zhong Zhuang , Hsiang-Jen Tseng
IPC: G06F30/392 , H01L21/768 , H01L27/118 , H01L27/02
Abstract: An integrated circuit designing system includes a non-transitory storage medium, the non-transitory storage medium being encoded with a layout of a standard cell corresponding to a predetermined manufacturing process, the predetermined manufacturing process having a nominal minimum pitch of metal lines along a predetermined direction, the layout of the standard cell having a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The integrated circuit designing system further includes a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.
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公开(公告)号：US09659129B2
公开(公告)日：2017-05-23
申请号：US14253205
申请日：2014-04-15
Inventor： Shang-Chih Hsieh , Hui-Zhong Zhuang , Ting-Wei Chiang , Chun-Fu Chen , Hsiang-Jen Tseng
IPC: H01L23/50 , G06F17/50 , H01L21/768 , H01L27/118 , H01L27/02
CPC classification number: G06F17/5072 , H01L21/768 , H01L27/0207 , H01L27/11807 , H01L2027/11875 , H01L2924/0002 , H01L2924/00
Abstract: An integrated circuit, manufactured by a process having a nominal minimum pitch of metal lines, includes a plurality of metal lines and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines extends along a first direction, and the plurality of metal lines are separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. At least one of the plurality of standard cells has a cell height along the second direction, and the cell height is a non-integral multiple of the nominal minimum pitch.
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