公开(公告)号：US20180166285A1

公开(公告)日：2018-06-14

申请号：US15730934

申请日：2017-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Ling LEE ,  Shing-Chyang PAN ,  Keng-Chu LIN ,  Wen-Cheng YANG ,  Chih-Tsung LEE ,  Victor Y. LU

IPC: H01L21/285 ,  H01L21/3065 ,  H01L21/8234

CPC classification number: H01L21/2855 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/3065 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/823437

Abstract: A method for forming a semiconductor device structure is provided. The method includes disposing a semiconductor substrate in a physical vapor deposition (PVD) chamber. The method also includes introducing a plasma-forming gas into the PVD chamber, and the plasma-forming gas contains an oxygen-containing gas. The method further includes applying a radio frequency (RF) power to a metal target in the PVD chamber to excite the plasma-forming gas to generate plasma. In addition, the method includes directing the plasma towards the metal target positioned in the PVD chamber such that an etch stop layer is formed over the semiconductor substrate.

公开(公告)号：US20150235823A1

公开(公告)日：2015-08-20

申请号：US14183670

申请日：2014-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chien CHI ,  Shing-Chyang PAN ,  Kuan-Chia CHEN ,  Yao-Jen CHANG ,  Huang-Yi HUANG ,  Ching-Hua HSIEH

IPC: H01J37/34 ,  C23C14/35 ,  C23C14/50 ,  H01L21/285 ,  C23C14/24 ,  C23C14/54

CPC classification number: C23C14/35 ,  C23C14/3492 ,  C23C14/542 ,  H01J37/3405 ,  H01J37/3452 ,  H01J37/3455 ,  H01J37/3458

Abstract: Embodiments of a plasma apparatus are provided. The plasma apparatus includes a processing chamber and a wafer chuck disposed in the processing chamber. The plasma apparatus also includes a target element located over the wafer chuck and an electromagnet array located over the target element and having a number of electromagnets. Some of the electromagnets in a magnetic-field zone of the electromagnet array are enabled to generate a magnetic field adjacent to the target element. The magnetic-field zone is moved during a semiconductor manufacturing process.

Abstract translation: 提供了等离子体装置的实施例。 等离子体装置包括设置在处理室中的处理室和晶片卡盘。 等离子体装置还包括位于晶片卡盘上方的目标元件和位于目标元件上方并具有多个电磁体的电磁体阵列。 电磁体阵列的磁场区域中的一些电磁体能够产生与目标元件相邻的磁场。 磁场区在半导体制造过程中移动。

公开(公告)号：US20210119120A1

公开(公告)日：2021-04-22

申请号：US17112861

申请日：2020-12-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Tang WU ,  Szu-Ping TUNG ,  Szu-Hua WU ,  Shing-Chyang PAN ,  Meng-Yu WU

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, an aluminum nitride layer, an aluminum oxide layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The aluminum nitride layer extends along a top surface of the first dielectric layer and a top surface of the metal contact. The aluminum oxide layer extends along a top surface of the aluminum nitride layer. The second dielectric layer is over the aluminum oxide layer. The metal via passes through the second dielectric layer, the aluminum oxide layer, and the aluminum nitride layer and lands on the metal contact. The memory stack lands on the metal via.

公开(公告)号：US20200152864A1

公开(公告)日：2020-05-14

申请号：US16741557

申请日：2020-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Tang WU ,  Szu-Ping TUNG ,  Szu-Hua WU ,  Shing-Chyang PAN ,  Meng-Yu WU

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, a metal nitride layer, an etch stop layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The metal nitride layer spans the first dielectric layer and the metal contact. The etch stop layer extends along a top surface of the metal nitride layer, in which a thickness of the metal nitride layer is less than a thickness of the etch stop layer. The second dielectric layer is over the etch stop layer. The metal via passes through the second dielectric layer, the etch stop layer, and the metal nitride layer and lands on the metal contact. The memory stack is in contact with the metal via.

公开(公告)号：US20230073308A1

公开(公告)日：2023-03-09

申请号：US17984066

申请日：2022-11-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO, LTD.

Inventor： Jung-Tang WU ,  Szu-Ping TUNG ,  Szu-Hua WU ,  Shing-Chyang PAN ,  Meng-Yu WU

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A structure includes a substrate, a transistor, a contact, an oxygen-free etch stop layer, an oxygen-containing etch stop layer, a dielectric layer, and a via. The transistor is on the substrate. The contact is on a source/drain region of the transistor. The oxygen-free etch stop layer spans the contact. The oxygen-containing etch stop layer extends along a top surface of the oxygen-free etch stop layer. The dielectric layer is over the oxygen-containing etch stop layer. The via passes through the dielectric layer, the oxygen-containing etch stop layer, and the oxygen-free etch stop layer and lands on the contact. The memory stack lands on the via.

公开(公告)号：US20190157548A1

公开(公告)日：2019-05-23

申请号：US16059777

申请日：2018-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Tang WU ,  Szu-Ping TUNG ,  Szu-Hua WU ,  Shing-Chyang PAN ,  Meng-Yu WU

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A via structure, a MRAM device using the via structure and a method for fabricating the MRAM device are provided. In the method for fabricating the MRAM device, at first, a first dielectric layer is deposited over a transistor. Then, a contact is formed in the first dielectric layer and electrically connected to the transistor. Thereafter, a metal nitride layer is deposited over the first dielectric layer and the contact. Then, an etch stop layer is deposited over the metal nitride layer. Thereafter, a second dielectric layer is deposited over the etch stop layer. Then, a via structure is formed in the second dielectric layer, the etch stop layer, and the metal nitride layer and landing on the contact. Thereafter, a memory stack is formed over the via structure.

公开(公告)号：US20200144063A1

公开(公告)日：2020-05-07

申请号：US16730343

申请日：2019-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ya-Ling LEE ,  Shing-Chyang PAN ,  Keng-Chu LIN ,  Wen-Cheng YANG ,  Chih-Tsung LEE ,  Victor Y. LU

IPC: H01L21/285 ,  H01L21/8234 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/768

Abstract: A method for forming a semiconductor device structure is provided. The method includes disposing a semiconductor substrate in a physical vapor deposition (PVD) chamber and introducing a plasma-forming gas into the PVD chamber. The plasma-forming gas is an oxygen-containing gas. The method also includes applying a radio frequency (RF) power by a power source to a metal target in the PVD chamber to excite the plasma-forming gas to generate plasma. The metal target is directly electrically coupled to the power source. The method further includes directing the plasma towards the metal target positioned in the PVD chamber such that an etch stop layer is formed over the semiconductor substrate.