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    SEMICONDUCTOR MEMORY DEVICES HAVING CLOSELY SPACED BIT LINES
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES HAVING CLOSELY SPACED BIT LINES 审中-公开

    公开(公告)号：US20180350833A1

    公开(公告)日：2018-12-06

    申请号：US16039975

    申请日：2018-07-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaeduk Lee ,  Youngwoo PARK

    IPC: H01L27/11582 ,  H01L27/06 ,  H01L27/11573

    CPC classification number: H01L27/11582 ,  H01L27/0688 ,  H01L27/11573

    Abstract: The inventive concepts relate to a semiconductor memory device. The semiconductor memory device includes a substrate including a circuit region and first and second connection regions respectively disposed at both sides of the circuit region opposite to each other, a logic structure including a logic circuit disposed on the circuit region and a lower insulating layer covering the logic circuit, and a memory structure on the logic structure. The logic circuit includes a first page buffer disposed adjacently to the first connection region and a second page buffer disposed adjacently to the second connection region. The memory structure includes bit lines extending onto at least one of the first and second connection regions.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME
    4.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
    三维半导体存储器件及其制造方法

    公开(公告)号：US20140227841A1

    公开(公告)日：2014-08-14

    申请号：US14258436

    申请日：2014-04-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaegoo LEE ,  Kil-Su JEONG ,  Hansoo KIM ,  Youngwoo PARK

    IPC: H01L27/115

    CPC classification number: H01L23/52 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Example embodiments relate to a three-dimensional semiconductor memory device including an electrode structure on a substrate, the electrode structure including at least one conductive pattern on a lower electrode, and a semiconductor pattern extending through the electrode structure to the substrate. A vertical insulating layer may be between the semiconductor pattern and the electrode structure, and a lower insulating layer may be between the lower electrode and the substrate. The lower insulating layer may be between a bottom surface of the vertical insulating layer and a top surface of the substrate. Example embodiments related to methods for fabricating the foregoing three-dimensional semiconductor memory device.

    Abstract translation: 示例实施例涉及一种三维半导体存储器件，其包括在衬底上的电极结构，该电极结构包括在下电极上的至少一个导电图案，以及半导体图案，其延伸穿过该电极结构到该衬底。 垂直绝缘层可以在半导体图案和电极结构之间，下绝缘层可以位于下电极和衬底之间。 下绝缘层可以在垂直绝缘层的底表面和基板的顶表面之间。 与制造上述三维半导体存储器件的方法相关的示例实施例。

    SWITCHED CAPACITOR CIRCUIT AND BIDIRECTIONAL SWITCHING CONVERTER INCLUDING THE SAME
    5.
    发明申请
    SWITCHED CAPACITOR CIRCUIT AND BIDIRECTIONAL SWITCHING CONVERTER INCLUDING THE SAME 有权

    公开(公告)号：US20250062686A1

    公开(公告)日：2025-02-20

    申请号：US18806085

    申请日：2024-08-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungwoo LEE ,  Sungwoo MOON ,  Daewoong CHO ,  Youngwoo PARK ,  Jinwoo SO ,  Yonghwan CHO

    IPC: H02M3/07 ,  H02J7/00

    Abstract: A switched capacitor circuit includes first, third, fifth and seventh switches connected to each other, second, fourth, sixth and eighth switches connected to each other, one end of each of the first and second switches connected to an input node, ninth and tenth switches connected to each other, eleventh and twelfth switches connected to each other, thirteenth and fourteenth switches connected to each other, fifteenth and sixteenth switches connected to each other, a first capacitor between the first and ninth switches, a second capacitor between the second and fifteenth switches, a third capacitor between the third and eleventh switches, a fourth capacitor between the fourth and thirteenth switches, a fifth capacitor between the sixth and eleventh switches, and a sixth capacitor between the fifth and thirteenth switches, one end of each of the ninth, eleventh, thirteenth, fifteenth, seventh and eighth switches connected to an output node.

    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20140367764A1

    公开(公告)日：2014-12-18

    申请号：US14472952

    申请日：2014-08-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaegoo LEE ,  Youngwoo PARK ,  Jungdal CHOI

    IPC: H01L27/115 ,  H01L29/423 ,  H01L29/78

    CPC classification number: H01L27/11578 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/7827 ,  H01L29/7926

    Abstract: A method of fabricating a semiconductor memory device includes forming a mold stack on a substrate and the mold stack including first sacrificial layers and second sacrificial layers alternately stacked on the substrate. The method also includes forming a plurality of vertical channels that penetrate the mold stack and that contact the substrate, patterning the mold stack to form word line cuts between the vertical channels, the word line cuts exposing the substrate, removing one of the first and second sacrificial layers to form recessed regions in the mold stack, forming a data storage layer, at least a portion of the data storage layer being formed between the vertical channels and the gates, forming gates in the recessed regions, forming air gaps between the gates by removing the other of the first and second sacrificial layers, and forming an insulation layer pattern in the word line cuts.

    Abstract translation: 一种制造半导体存储器件的方法包括在衬底上形成模具堆叠，并且模具叠层包括交替层叠在衬底上的第一牺牲层和第二牺牲层。 该方法还包括形成多个垂直通道，其穿过模具叠层并与衬底接触，图案化模具叠层以形成垂直通道之间的字线切口，字线切割暴露衬底，去除第一和第二 牺牲层，以在模具堆叠中形成凹陷区域，形成数据存储层，数据存储层的至少一部分形成在垂直沟道和栅极之间，在凹陷区域中形成栅极，在栅极之间形成气隙，通过 去除第一和第二牺牲层中的另一个，并且在字线切割中形成绝缘层图案。

    MEMORY CARD, ELECTRONIC SYSTEM INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME
    8.
    发明公开
    MEMORY CARD, ELECTRONIC SYSTEM INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240062034A1

    公开(公告)日：2024-02-22

    申请号：US18130569

    申请日：2023-04-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Youngwoo PARK

    IPC: G06K19/077

    CPC classification number: G06K19/07732 ,  G06K19/07743 ,  G06K19/07745 ,  G06K19/07733

    Abstract: A memory card includes a case compliant with a first standard, corresponding to a first protocol, a card substrate embedded in the case, a plurality of external contact terminals, corresponding the first standard, on an upper surface of the card substrate and having at least a portion exposed outwardly of the case, and an integrated circuit package attached to the upper surface of the card substrate and including a plurality of package terminals corresponding to a second protocol. First external contact terminals, among the plurality of eternal contact terminals, may be electrically connected to first package terminals among the plurality of package terminals.

    STORAGE DEVICE AND METHOD OF OPERATION THEREOF
    9.
    发明申请
    STORAGE DEVICE AND METHOD OF OPERATION THEREOF 有权

    公开(公告)号：US20230007903A1

    公开(公告)日：2023-01-12

    申请号：US17708771

    申请日：2022-03-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Youngwoo PARK ,  Taeduk NAM

    IPC: G06F3/06

    Abstract: A storage device, including a printed circuit board including a connector including a plurality of pins capable of being coupled to an external host device, a controller socket, a first slot, a second slot, a third slot, and a fourth slot; a first universal flash storage (UFS) device, a second UFS device, a third UFS device, and a fourth UFS device, wherein each UFS device of the first to fourth UFS devices is removably installed in a corresponding slot of the first to fourth slots; and a storage controller mounted in the controller socket, and configured to control the first to fourth UFS devices, wherein the first UFS device and the second UFS device are configured to communicate with the storage controller through a first channel, and the third UFS device and the fourth UFS device are configured to communicate with the storage controller through a second channel

    MEMORY CARD
    10.
    发明申请
    MEMORY CARD 有权

    公开(公告)号：US20220189915A1

    公开(公告)日：2022-06-16

    申请号：US17377865

    申请日：2021-07-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Youngwoo PARK

    IPC: H01L25/065 ,  H01L23/00 ,  G11C11/56

    Abstract: A memory card includes an upper case, a lower case, and an integrated circuit package between the upper case and the lower case. The integrated circuit package includes a memory stacked chip on a panel substrate, and the memory stacked chip includes a base memory stacked chip and an additional memory stacked chip stacked on the base memory stacked chip. The integrated circuit package includes a frequency boosting interface chip on the panel substrate and electrically connected to the memory stacked chip, and a controller chip on the panel substrate and electrically connected to the memory stacked chip and the frequency boosting interface chip.

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