公开(公告)号：US20220068424A1

公开(公告)日：2022-03-03

申请号：US17318234

申请日：2021-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongho LEE ,  Kwangjin LEE ,  Hee Hyun NAM ,  Jaeho SHIN ,  Youngkwang YOO

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18 ,  G11C7/10

Abstract: Disclosed is a method of performing, at a controller, an access to a memory device, which includes transmitting, at the controller, a first command signal, a first address signal, and a first swizzling signal to the memory device, selecting first data bits stored in a memory cell array of the memory device based on the first command signal and the first address signal, and sequentially outputting, at the memory device, at least a part of the first data bits to the controller in a burst manner, based on the first swizzling signal.

公开(公告)号：US20170235524A1

公开(公告)日：2017-08-17

申请号：US15421514

申请日：2017-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngkwang YOO ,  Youngjin CHO ,  Han-Ju LEE ,  JinHyeok CHOI

IPC: G06F3/06 ,  G06F12/0868

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0685 ,  G06F12/0868 ,  G06F2212/1016 ,  G06F2212/202 ,  G11C8/12 ,  G11C2207/2245

Abstract: A nonvolatile memory module may include a nonvolatile memory device, a nonvolatile memory controller configured to control the nonvolatile memory device, a volatile memory device configured as a cache memory of the nonvolatile memory device, and a module controller configured to receive a command and an address from an external device, external to the nonvolatile memory module, and to send a volatile memory command and a volatile memory address to the volatile memory device through a first bus and a nonvolatile memory command and a nonvolatile memory address to the controller through a second bus in response to the received command and address. The volatile memory device is configured to load two or more cache data on each of two or more memory data line groups and two or more tags on each of two or more tag data line groups in response to the volatile memory address.

公开(公告)号：US20170062040A1

公开(公告)日：2017-03-02

申请号：US15249333

申请日：2016-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNGJIN CHO ,  JAEGEUN PARK ,  Youngkwang YOO

IPC: G11C11/4074 ,  G11C7/10 ,  G06F1/32 ,  G11C11/406

CPC classification number: G11C11/4074 ,  G06F1/3287 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4067

Abstract: A dynamic random access memory (DRAM) device includes a memory cell array including a plurality of memory cells, a refresh controller configured to perform a plurality of refresh operations on the plurality of memory cells in response to a plurality of refresh commands from an external device, and a refresh counter configured to count a number of the refresh commands for a fixed period of time and compare the counted number with a threshold. The refresh counter is configured to generate a power failure signal to cause the DRAM device to enter a power failure mode in response to the comparison of the counted number with the threshold. The refresh controller is configured to perform a refresh operation on the plurality of memory cells without control of the external device in the power failure mode.

Abstract translation: 动态随机存取存储器（DRAM）装置包括包括多个存储器单元的存储单元阵列，刷新控制器，被配置为响应于来自外部设备的多个刷新命令对所述多个存储器单元执行多个刷新操作 以及刷新计数器，被配置为在固定时间段内对多个刷新命令进行计数，并将计数的数量与阈值进行比较。 刷新计数器被配置为响应于计数的数量与阈值的比较而产生电源故障信号以使DRAM设备进入电源故障模式。 刷新控制器被配置为在电源故障模式下不对外部设备进行控制，对多个存储单元执行刷新操作。