公开(公告)号：US08748239B2

公开(公告)日：2014-06-10

申请号：US13956482

申请日：2013-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil Kim ,  Young-Goan Jang ,  Dong-Won Kim ,  Hag-Ju Cho

IPC: H01L21/335 ,  H01L21/8232

CPC classification number: H01L21/28008 ,  H01L21/28123 ,  H01L21/76 ,  H01L21/76232 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: A method of fabricating a gate includes sequentially forming an insulation layer and a conductive layer on substantially an entire surface of a substrate. The substrate has a device isolation layer therein and a top surface of the device isolation layer is higher than a top surface of the substrate. The method includes planarizing a top surface of the conductive layer and forming a gate electrode by patterning the insulation layer and the conductive layer.

Abstract translation: 制造栅极的方法包括在基板的基本上整个表面上依次形成绝缘层和导电层。 衬底在其中具有器件隔离层，器件隔离层的顶表面高于衬底的顶表面。 该方法包括通过图案化绝缘层和导电层来平坦化导电层的顶表面并形成栅电极。