公开(公告)号：US20250048723A1

公开(公告)日：2025-02-06

申请号：US18645844

申请日：2024-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo LEE ,  Sutae KIM

IPC: H01L27/088 ,  H01L23/48 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a substrate having first and second surfaces; an active pattern extending on the first surface of the substrate, the active pattern having first and second conductivity-type impurity regions, the first and second conductivity-type impurity regions in contact with each other; semiconductor patterns stacked on a portion of the active pattern between the first and second conductivity-type impurity regions; an inactive gate structure extending across the portion of the active pattern between the first and second conductivity-type impurity regions, the inactive gate structure surrounding the semiconductor patterns; a first contact passing through the substrate from the second surface of the substrate and connected to the first conductivity-type impurity region; and a second contact passing through the substrate from the second surface of the substrate and connected to the second conductivity-type impurity region.

公开(公告)号：US20230097159A1

公开(公告)日：2023-03-30

申请号：US17839724

申请日：2022-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo LEE ,  Chunyub PARK ,  Sutae KIM

IPC: H01L21/28 ,  H01L21/8234

Abstract: A method of manufacturing a semiconductor device may include forming a hardmask layer on gate lines and intergate insulating portions alternately arranged; respectively forming mandrel lines on regions of the hardmask layer, corresponding to every other one of the intergate insulating portions; conformally forming a spacer material layer, having a thickness corresponding to a width of the gate lines, on the hardmask layer; forming a mandrel material layer on the spacer material layer; removing a portion of the mandrel material layer to expose portions of the spacer material layer on an upper surface and a side surface of the mandrel line; removing the exposed portions of the spacer material layer to provide the mandrel lines and stacked mandrel patterns; and forming an opening in the hardmask layer, which exposes a gate-cut region of the gate lines, using the mandrel lines and the stacked mandrel patterns as a mask.

公开(公告)号：US20250014995A1

公开(公告)日：2025-01-09

申请号：US18663381

申请日：2024-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo LEE ,  Hojun CHOI ,  Sutae KIM ,  Hyelim KIM ,  Seung CHOI

IPC: H01L23/528 ,  H01L23/522 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a plurality of active patterns respectively extending on a substrate in a first direction, a separation pattern extending on the substrate in a second direction, and dividing each of the plurality of active patterns into first and second active patterns, the separation pattern including a first separation pattern and a second separation pattern, the second separation pattern being shifted from the first separation pattern in the first direction to partially overlap the first separation pattern in the second direction, first and second dummy gate structures on first and second sides of the separation pattern, respectively, and extending along corresponding end portions of the first and second active patterns in the second direction, respectively, and a plurality of first and second gate structures crossing portions of the first and second active patterns, respectively, and extending in the second direction.

公开(公告)号：US20240321726A1

公开(公告)日：2024-09-26

申请号：US18419715

申请日：2024-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo LEE ,  Yubo QIAN ,  Hyunjae KANG ,  Gyeongseop KIM ,  Sutae KIM ,  Jaeyoung PARK ,  Jeonwon JEONG

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/088

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/088 ,  H01L27/0886

Abstract: An integrated circuit device includes a first conductive pattern disposed on a substrate, a second conductive pattern surrounding a portion of the first conductive pattern and covering a lower portion of a sidewall of the first conductive pattern, an upper insulation structure on the first conductive pattern and the second conductive pattern, and an upper conductive pattern penetrating through the upper insulation structure and extending in a vertical direction, wherein the upper conductive pattern includes a main plug portion overlapping the first conductive pattern and the second conductive pattern in the vertical direction, and a vertical extension extending from a portion of the main plug portion toward the substrate, covering an upper of the upper sidewall of the first conductive pattern, and overlapping the second conductive pattern in the vertical direction, and a dummy contact is formed on a single diffusion break region on the substrate.

公开(公告)号：US20240274598A1

公开(公告)日：2024-08-15

申请号：US18500636

申请日：2023-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo LEE ,  Hojun CHOI ,  Sutae KIM

IPC: H01L27/06 ,  H01L21/306 ,  H01L23/48 ,  H01L23/522 ,  H01L29/732

CPC classification number: H01L27/0623 ,  H01L21/30625 ,  H01L23/481 ,  H01L23/5226 ,  H01L29/7322

Abstract: The present disclosure relates to an integrated circuit element and a manufacturing method thereof. An integrated circuit element may include a substrate including a first region and a second region, a first element in the first region of the substrate and configured to generate an electric field in a horizontal direction, and a second element in the second region of the substrate and configured to generate an electric field is formed in a vertical direction, wherein a thickness of the second region of the substrate is thicker than a thickness of the first region.

公开(公告)号：US20200321355A1

公开(公告)日：2020-10-08

申请号：US16574339

申请日：2019-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo JEONG ,  Jiwook KWON ,  Sutae KIM ,  Hyelim KIM

IPC: H01L27/118 ,  H01L27/02

Abstract: A semiconductor device including first and second active regions extending in a first direction; a field region between the first and second active regions; a gate structure including an upper gate electrode overlapping the first active region and extending in a second direction crossing the first direction, and a lower gate electrode overlapping the second active region, extending in the second direction, and on a same line as the upper gate electrode; a gate isolation layer between the upper and lower gate electrodes; source/drain regions on respective sides of the upper gate electrode; a contact jumper crossing the upper gate electrode in the second active region and electrically connecting the source/drain regions; and a first upper contact extending in the second direction in the field region and overlapping the lower gate electrode and the gate isolation layer, wherein the upper gate electrode is a dummy gate electrode.