公开(公告)号：US20240162226A1

公开(公告)日：2024-05-16

申请号：US18416375

申请日：2024-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonah NAM ,  Byungju KANG ,  Byungsung KIM ,  Hyelim KIM ,  Sungho PARK ,  Yubo QIAN

IPC: H01L27/088 ,  H01L23/538 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/088 ,  H01L23/5384 ,  H01L29/0653 ,  H01L29/4232

Abstract: A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.

公开(公告)号：US20220375932A1

公开(公告)日：2022-11-24

申请号：US17880819

申请日：2022-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonah NAM ,  Byungju KANG ,  Byungsung KIM ,  Hyelim KIM ,  Sungho PARK ,  Yubo QIAN

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L23/538

Abstract: A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.

公开(公告)号：US20250014995A1

公开(公告)日：2025-01-09

申请号：US18663381

申请日：2024-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo LEE ,  Hojun CHOI ,  Sutae KIM ,  Hyelim KIM ,  Seung CHOI

IPC: H01L23/528 ,  H01L23/522 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a plurality of active patterns respectively extending on a substrate in a first direction, a separation pattern extending on the substrate in a second direction, and dividing each of the plurality of active patterns into first and second active patterns, the separation pattern including a first separation pattern and a second separation pattern, the second separation pattern being shifted from the first separation pattern in the first direction to partially overlap the first separation pattern in the second direction, first and second dummy gate structures on first and second sides of the separation pattern, respectively, and extending along corresponding end portions of the first and second active patterns in the second direction, respectively, and a plurality of first and second gate structures crossing portions of the first and second active patterns, respectively, and extending in the second direction.

公开(公告)号：US20210175232A1

公开(公告)日：2021-06-10

申请号：US17024044

申请日：2020-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonah NAM ,  Byungju KANG ,  Byungsung KIM ,  Hyelim KIM ,  Sungho PARK ,  Yubo QIAN

IPC: H01L27/088 ,  H01L23/538 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.

公开(公告)号：US20200321355A1

公开(公告)日：2020-10-08

申请号：US16574339

申请日：2019-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo JEONG ,  Jiwook KWON ,  Sutae KIM ,  Hyelim KIM

IPC: H01L27/118 ,  H01L27/02

Abstract: A semiconductor device including first and second active regions extending in a first direction; a field region between the first and second active regions; a gate structure including an upper gate electrode overlapping the first active region and extending in a second direction crossing the first direction, and a lower gate electrode overlapping the second active region, extending in the second direction, and on a same line as the upper gate electrode; a gate isolation layer between the upper and lower gate electrodes; source/drain regions on respective sides of the upper gate electrode; a contact jumper crossing the upper gate electrode in the second active region and electrically connecting the source/drain regions; and a first upper contact extending in the second direction in the field region and overlapping the lower gate electrode and the gate isolation layer, wherein the upper gate electrode is a dummy gate electrode.