公开(公告)号：US20240162226A1

公开(公告)日：2024-05-16

申请号：US18416375

申请日：2024-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonah NAM ,  Byungju KANG ,  Byungsung KIM ,  Hyelim KIM ,  Sungho PARK ,  Yubo QIAN

IPC: H01L27/088 ,  H01L23/538 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/088 ,  H01L23/5384 ,  H01L29/0653 ,  H01L29/4232

Abstract: A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.

公开(公告)号：US20210175232A1

公开(公告)日：2021-06-10

申请号：US17024044

申请日：2020-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonah NAM ,  Byungju KANG ,  Byungsung KIM ,  Hyelim KIM ,  Sungho PARK ,  Yubo QIAN

IPC: H01L27/088 ,  H01L23/538 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.

公开(公告)号：US20220375932A1

公开(公告)日：2022-11-24

申请号：US17880819

申请日：2022-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonah NAM ,  Byungju KANG ,  Byungsung KIM ,  Hyelim KIM ,  Sungho PARK ,  Yubo QIAN

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L23/538

Abstract: A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.