公开(公告)号：US20180129773A1

公开(公告)日：2018-05-10

申请号：US15610751

申请日：2017-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjun PARK ,  Byung-Sung KIM ,  CHULHONG PARK ,  Chunyub PARK

IPC: G06F17/50 ,  H01L21/8234 ,  H01L27/02

CPC classification number: G06F17/5081 ,  G06F2217/12 ,  H01L21/823437 ,  H01L27/0207

Abstract: A design method of a semiconductor integrated circuit layout and a method of fabricating a semiconductor device, the design method including selecting a first cell layout including at least one first gate pattern; selecting a second cell layout including at least one second gate pattern, the at least one second gate pattern having a gate length that is different from a gate length of the at least one first gate pattern; producing a pattern layout from the first and second cell layouts; and producing a mask layout selectively overlapping the first cell layout on the pattern layout.

公开(公告)号：US20230097159A1

公开(公告)日：2023-03-30

申请号：US17839724

申请日：2022-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo LEE ,  Chunyub PARK ,  Sutae KIM

IPC: H01L21/28 ,  H01L21/8234

Abstract: A method of manufacturing a semiconductor device may include forming a hardmask layer on gate lines and intergate insulating portions alternately arranged; respectively forming mandrel lines on regions of the hardmask layer, corresponding to every other one of the intergate insulating portions; conformally forming a spacer material layer, having a thickness corresponding to a width of the gate lines, on the hardmask layer; forming a mandrel material layer on the spacer material layer; removing a portion of the mandrel material layer to expose portions of the spacer material layer on an upper surface and a side surface of the mandrel line; removing the exposed portions of the spacer material layer to provide the mandrel lines and stacked mandrel patterns; and forming an opening in the hardmask layer, which exposes a gate-cut region of the gate lines, using the mandrel lines and the stacked mandrel patterns as a mask.

公开(公告)号：US20190286785A1

公开(公告)日：2019-09-19

申请号：US16432139

申请日：2019-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjun PARK ,  Byung-Sung KIM ,  Chulhong PARK ,  Chunyub PARK

IPC: G06F17/50 ,  H01L27/02

Abstract: A design method of a semiconductor integrated circuit layout and a method of fabricating a semiconductor device, the design method including selecting a first cell layout including at least one first gate pattern; selecting a second cell layout including at least one second gate pattern, the at least one second gate pattern having a gate length that is different from a gate length of the at least one first gate pattern; producing a pattern layout from the first and second cell layouts; and producing a mask layout selectively overlapping the first cell layout on the pattern layout.