公开(公告)号：US20240292600A1

公开(公告)日：2024-08-29

申请号：US18240516

申请日：2023-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Tae RYU ,  Byong-Deok CHOI ,  Sungwon YOO ,  Wonsok LEE ,  Yongsang YOO

IPC: H10B12/00 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

CPC classification number: H10B12/482 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  H01L28/90 ,  H10B12/312 ,  H10B12/315 ,  H10B12/50

Abstract: A memory device includes a first memory cell connected to a first bitline and a second memory cell connected to a second bitline, wherein the first memory cell may include a first access transistor including one end connected to the first bitline, and a first capacitor including one electrode connected to another end of the first access transistor and another electrode connected to the second bitline, and the first access transistor may include an oxide semiconductor.

公开(公告)号：US20210358913A1

公开(公告)日：2021-11-18

申请号：US17092593

申请日：2020-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Huijung KIM ,  Satoru YAMADA ,  Sungwon YOO ,  Kyunghwan LEE ,  Jaeho HONG

IPC: H01L27/102 ,  H01L29/74

Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.

公开(公告)号：US20220367721A1

公开(公告)日：2022-11-17

申请号：US17694903

申请日：2022-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Kyeong JEONG ,  Min Tae RYU ,  Hyeon Joo SEUL ,  Sungwon YOO ,  Wonsok LEE ,  Min Hee CHO ,  Jae Seok HUR

IPC: H01L29/786

Abstract: Provided is a semiconductor memory device comprising a bit line extending in a first direction, a channel pattern on the bit line and including a first oxide semiconductor layer in contact with the bit line and a second oxide semiconductor layer on the first oxide semiconductor layer, wherein each of the first and second oxide semiconductor layers includes a horizontal part parallel to the bit line and first and second vertical parts that vertically protrude from the horizontal part, first and second word lines between the first and second vertical parts of the second oxide semiconductor layer and on the horizontal part of the second oxide semiconductor layer, and a gate dielectric pattern between the channel pattern and the first and second word lines. A thickness of the second oxide semiconductor layer is greater than that of the first oxide semiconductor layer.

公开(公告)号：US20220029095A1

公开(公告)日：2022-01-27

申请号：US17192093

申请日：2021-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Hyeoungwon SEO ,  Sungwon YOO ,  Kyunghwan LEE ,  Jaeho HONG

IPC: H01L45/00 ,  H01L27/24 ,  H01L23/00

Abstract: A vertical variable resistance memory device including gate electrodes spaced apart from each other in a first direction on a substrate, each of the gate electrodes including graphene and extending in a second direction, the first direction being substantially perpendicular to an upper surface of the substrate and the second direction being substantially parallel to the upper surface of the substrate; first insulation patterns between the gate electrodes, each of the first insulation patterns including boron nitride (BN); and at least one pillar structure extending in the first direction through the gate electrodes and the first insulation patterns on the substrate, wherein the at least one pillar structure includes a vertical gate electrode extending in the first direction; and a variable resistance pattern on a sidewall of the vertical gate electrode.

公开(公告)号：US20250142806A1

公开(公告)日：2025-05-01

申请号：US19003119

申请日：2024-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Ilgweon KIM ,  Hyeoungwon SEO ,  Sungwon YOO ,  Jaeho HONG

IPC: H10B12/00

Abstract: A semiconductor memory device includes a word line extending in a vertical direction, a semiconductor pattern having a ring-shaped horizontal cross-section that extends around the word line, a bit line at a first end of the semiconductor pattern, and a capacitor structure at second end of the semiconductor pattern. The capacitor structure includes a lower electrode layer electrically connected to the second end of the semiconductor pattern, having a ring-shaped horizontal cross-section, and including a connector extending in the vertical direction. A first segment extends in a horizontal direction from an upper end of the connector, and a second segment extends in the horizontal direction from a lower end of the connector. An upper electrode layer surrounded by the lower electrode layer, extends in the vertical direction, and a capacitor dielectric layer is between the lower electrode layer and the upper electrode layer.

公开(公告)号：US20210359200A1

公开(公告)日：2021-11-18

申请号：US17110524

申请日：2020-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Kohji KANAMORI ,  Unghwan PI ,  Hyuncheol KIM ,  Sungwon YOO ,  Jaeho HONG

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/10 ,  H01L43/02 ,  G11C11/16 ,  H01L23/522

Abstract: A memory device includes a magnetic track layer extending on a substrate, the magnetic track layer having a folded structure that is two-dimensionally villi-shaped, a plurality of reading units including a plurality of fixed layers and a tunnel barrier layer between the magnetic track layer and each of the plurality of fixed layers, and a plurality of bit lines extending on different ones of the plurality of reading units, the plurality of reading units being between the magnetic track layer and corresponding ones of the plurality of bit lines.

公开(公告)号：US20250113590A1

公开(公告)日：2025-04-03

申请号：US18976522

申请日：2024-12-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Huijung KIM ,  Satoru YAMADA ,  Sungwon YOO ,  Kyunghwan LEE ,  Jaeho HONG

IPC: H01L29/74 ,  H10B12/10

Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.

公开(公告)号：US20230307551A1

公开(公告)日：2023-09-28

申请号：US18092973

申请日：2023-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwon YOO ,  Yongseok KIM ,  Min Tae RYU ,  Huije RYU ,  Yongjin LEE ,  Wonsok LEE ,  Min Hee CHO

IPC: H01L29/786 ,  H10B12/00 ,  H01L27/146 ,  H01L29/417

CPC classification number: H01L29/78693 ,  H01L27/10814 ,  H01L27/14616 ,  H01L29/41733 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a channel layer between the substrate and the gate electrode, a source electrode in contact with a first sidewall of the channel layer, and a drain electrode in contact with a second sidewall of the channel layer. The second sidewall is opposite to the first sidewall. The channel layer includes a first channel pattern in contact with one of the source electrode and the drain electrode, and a second channel pattern between the first channel pattern and the gate electrode. The first channel pattern and the second channel pattern includes oxide semiconductor materials different from each other. A portion of the source electrode and a portion of the drain electrode overlap a portion of the gate electrode.

公开(公告)号：US20210225842A1

公开(公告)日：2021-07-22

申请号：US16999378

申请日：2020-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Satoru YAMADA ,  Sungwon YOO ,  Kyunghwan LEE ,  Jaeho HONG

IPC: H01L27/102 ,  H01L29/24

Abstract: A semiconductor memory device may include a first electrode and a second electrode, which are spaced apart from each other in a first direction, and a first semiconductor pattern, which is in contact with both of the first and second electrodes. The first semiconductor pattern may include first to fourth sub-semiconductor patterns, which are sequentially disposed in the first direction. The first and fourth sub-semiconductor patterns may be in contact with the first and second electrodes, respectively. The first and third sub-semiconductor patterns may be of a first conductivity type, and the second and fourth sub-semiconductor patterns may be of a second conductivity type different from the first conductivity type. Each of the first to fourth sub-semiconductor patterns may include a transition metal and a chalcogen element.

公开(公告)号：US20230009575A1

公开(公告)日：2023-01-12

申请号：US17690371

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee CHO ,  Mintae RYU ,  Sungwon YOO ,  Wonsok LEE ,  Hyunmog PARK ,  Kiseok LEE

IPC: H01L29/786

Abstract: A semiconductor device including a conductive line on a substrate, a first gate electrode on the conductive line, a second gate electrode separated by a gate isolation insulating layer on the first gate electrode, a first channel layer on a side surface of the first gate electrode, with a first gate insulating layer therebetween, a first source/drain region on another side surface of the first gate electrode, a second channel layer on another side surface of the second gate electrode on a side that is opposite to the first channel layer, with a second gate insulating layer therebetween, a second source/drain region on the second channel layer, and a third source/drain region on the first channel layer and on a side surface of the second gate electrode on a same side as the first channel layer may be provided.