Semiconductor device including dummy metal

    公开(公告)号:US10032780B2

    公开(公告)日:2018-07-24

    申请号:US15139444

    申请日:2016-04-27

    Abstract: A semiconductor device may include a plurality of dummy wirings formed on a substrate at different vertical levels and electrically floated and a plurality of dummy contact plugs each electrically connected between two adjacent dummy wirings of the plurality of dummy wiring of the plurality of dummy wirings. No dummy wiring of the plurality of dummy wirings is electrically connected to a terminal of any one of a plurality of transistors included in the substrate.

    Methods for fabricating semiconductor devices with wet etching
    2.
    发明授权
    Methods for fabricating semiconductor devices with wet etching 有权
    用湿蚀刻制造半导体器件的方法

    公开(公告)号:US09337105B1

    公开(公告)日:2016-05-10

    申请号:US14732884

    申请日:2015-06-08

    Abstract: A method for fabricating a semiconductor device is provided. The method for fabricating a semiconductor device includes forming transistors on a semiconductor substrate, each of the transistors having a gate structure and source/drain regions, forming an oxide film on the transistors, forming a mask film pattern on the oxide film, the mask film pattern comprising a first pattern having a first width and a second pattern having a second width different from the first width, removing a part of the oxide film using the mask film pattern to form first and second trenches, filling the first and second trenches with a nitride film, removing the rest part of the oxide film to form third and fourth trenches, and forming conductive contacts by filling the third and fourth trenches. A top width of each of the third trenches is equal to the first width, and a top width of each of the fourth trenches is equal to the second width.

    Abstract translation: 提供一种制造半导体器件的方法。 半导体器件的制造方法包括在半导体衬底上形成晶体管,每个晶体管具有栅极结构和源极/漏极区域,在晶体管上形成氧化物膜,在氧化膜上形成掩模膜图案,掩模膜 图案包括具有第一宽度的第一图案和具有不同于第一宽度的第二宽度的第二图案,使用掩模膜图案去除一部分氧化膜以形成第一和第二沟槽,用第一和第二沟槽填充第一和第二沟槽 去除氧化膜的其余部分以形成第三和第四沟槽,并且通过填充第三和第四沟槽形成导电接触。 每个第三沟槽的顶部宽度等于第一宽度,并且每个第四沟槽的顶部宽度等于第二宽度。

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