公开(公告)号：US11942477B2

公开(公告)日：2024-03-26

申请号：US18117594

申请日：2023-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun Ki Min

IPC: H01L27/088 ,  H01L21/762 ,  H01L29/423

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L29/42372

Abstract: A semiconductor device including a gate separation region is provided. The semiconductor device includes an isolation region between active regions; interlayer insulating layers on the isolation region; gate line structures overlapping the active regions, disposed on the isolation region, and having end portions facing each other; and a gate separation region disposed on the isolation region, and disposed between the end portions of the gate line structures facing each other and between the interlayer insulating layers. The gate separation region comprises a gap fill layer and a buffer structure, the buffer structure includes a buffer liner disposed between the gap fill layer and the isolation region, between the end portions of the gate line structures facing each other and side surfaces of the gap fill layer, and between the interlayer insulating layers and the side surfaces of the gap fill layer.

公开(公告)号：US11600617B2

公开(公告)日：2023-03-07

申请号：US17102659

申请日：2020-11-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun Ki Min

IPC: H01L29/423 ,  H01L21/762 ,  H01L27/088

Abstract: A semiconductor device including a gate separation region is provided. The semiconductor device includes an isolation region between active regions; interlayer insulating layers on the isolation region; gate line structures overlapping the active regions, disposed on the isolation region, and having end portions facing each other; and a gate separation region disposed on the isolation region, and disposed between the end portions of the gate line structures facing each other and between the interlayer insulating layers. The gate separation region comprises a gap fill layer and a buffer structure, the buffer structure includes a buffer liner disposed between the gap fill layer and the isolation region, between the end portions of the gate line structures facing each other and side surfaces of the gap fill layer, and between the interlayer insulating layers and the side surfaces of the gap fill layer.

公开(公告)号：US20220069092A1

公开(公告)日：2022-03-03

申请号：US17216903

申请日：2021-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun Ki Min ,  Chae Ho Na ,  Sang Koo Kang ,  Ik Soo Kim ,  Dong Hyun Roh

IPC: H01L29/417 ,  H01L27/092 ,  H01L23/535 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device may include first and second fin-shaped patterns on a substrate, that extend in a first direction, and are spaced apart from each other in a second direction. A first epitaxial pattern may be on the first fin-shaped pattern, and a second epitaxial pattern may be on the second fin-shaped pattern. A field insulating layer may be on the substrate, and may cover a sidewall of the first fin-shaped pattern, a sidewall of the second fin-shaped pattern, a part of a sidewall of the first epitaxial pattern, and a part of a sidewall of the second epitaxial pattern. The top surface of the field insulating layer may be higher than the bottom surface of the first epitaxial pattern and the bottom surface of the second epitaxial pattern.

公开(公告)号：US20220393030A1

公开(公告)日：2022-12-08

申请号：US17667608

申请日：2022-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chae Ho NA ,  Sung Soo Kim ,  Sun Ki Min ,  Dong Hyun Roh

IPC: H01L29/78 ,  H01L29/417

Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a first fin-type pattern and a second fin-type pattern on a substrate, a first epitaxial pattern on the first fin-type pattern, a second epitaxial pattern on the second fin-type pattern, and a lower field insulating film on the substrate and extends on a sidewall of the first fin-type pattern and a sidewall of the second fin-type pattern, wherein the lower field insulating film includes a protrusion protruding in a third direction. The protrusion of the lower field insulating film may be between the first fin-type pattern and the second fin-type pattern, and a vertical level of a top surface of the protrusion of the lower field insulating film increases and then decreases with increasing distance from the sidewall of the first fin-type pattern.

公开(公告)号：US10854601B2

公开(公告)日：2020-12-01

申请号：US16194468

申请日：2018-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun Ki Min

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L29/165 ,  H01L21/762

Abstract: A semiconductor device including a gate separation region is provided. The semiconductor device includes an isolation region between active regions; interlayer insulating layers on the isolation region; gate line structures overlapping the active regions, disposed on the isolation region, and having end portions facing each other; and a gate separation region disposed on the isolation region, and disposed between the end portions of the gate line structures facing each other and between the interlayer insulating layers. The gate separation region comprises a gap fill layer and a buffer structure, the buffer structure includes a buffer liner disposed between the gap fill layer and the isolation region, between the end portions of the gate line structures facing each other and side surfaces of the gap fill layer, and between the interlayer insulating layers and the side surfaces of the gap fill layer.

公开(公告)号：US12218131B2

公开(公告)日：2025-02-04

申请号：US18591687

申请日：2024-02-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun Ki Min

IPC: H01L27/088 ,  H01L21/762 ,  H01L29/423

Abstract: A semiconductor device including a gate separation region is provided. The semiconductor device includes an isolation region between active regions; interlayer insulating layers on the isolation region; gate line structures overlapping the active regions, disposed on the isolation region, and having end portions facing each other; and a gate separation region disposed on the isolation region, and disposed between the end portions of the gate line structures facing each other and between the interlayer insulating layers. The gate separation region comprises a gap fill layer and a buffer structure, the buffer structure includes a buffer liner disposed between the gap fill layer and the isolation region, between the end portions of the gate line structures facing each other and side surfaces of the gap fill layer, and between the interlayer insulating layers and the side surfaces of the gap fill layer.

公开(公告)号：US20220310811A1

公开(公告)日：2022-09-29

申请号：US17456474

申请日：2021-11-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun Ki Min

IPC: H01L29/417 ,  H01L27/06 ,  H01L27/088

Abstract: A semiconductor includes a gate structure on a substrate and including a gate electrode, a source/drain pattern on a side surface of the gate electrode, a source/drain contact connected to the source/drain pattern, a first etching stop film structure on the source/drain contact and the gate structure, the first etching stop film structure including a first lower etching stop film and a silicon nitride film on the first lower etching stop film, and a first via plug inside the first etching stop film structure and connected to the source/drain contact, wherein the first lower etching stop film includes aluminum, and wherein an upper surface of the silicon nitride film is on a same plane as an upper surface of the first via plug.

公开(公告)号：US10128240B2

公开(公告)日：2018-11-13

申请号：US15807012

申请日：2017-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun Ki Min ,  Sang Koo Kang ,  Koung Min Ryu ,  Gi Gwan Park

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/311 ,  H01L21/8234 ,  H01L23/535 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a substrate including first to third regions, wherein the third region is positioned in a first direction between the first and second regions, a fin protruding on the substrate and extending in the first direction, first and second gate structures respectively formed on the fin in the first and second regions, first and second spacers formed with spacing apart from each other on the fin in the third region. The first and second spacers are sloped in a direction away from each other, and the first and second spacers and an upper surface of the fin define a plurality of acute angles, the first and second spacers defining a recess, the fin and the first and second spacers defining sidewalls of the recess, and a device isolating film substantially filling the recess.

公开(公告)号：US12237386B2

公开(公告)日：2025-02-25

申请号：US17456474

申请日：2021-11-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun Ki Min

IPC: H01L29/417 ,  H01L27/06 ,  H01L27/088

Abstract: A semiconductor includes a gate structure on a substrate and including a gate electrode, a source/drain pattern on a side surface of the gate electrode, a source/drain contact connected to the source/drain pattern, a first etching stop film structure on the source/drain contact and the gate structure, the first etching stop film structure including a first lower etching stop film and a silicon nitride film on the first lower etching stop film, and a first via plug inside the first etching stop film structure and connected to the source/drain contact, wherein the first lower etching stop film includes aluminum, and wherein an upper surface of the silicon nitride film is on a same plane as an upper surface of the first via plug.

公开(公告)号：US12170281B2

公开(公告)日：2024-12-17

申请号：US17706815

申请日：2022-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun Ki Min ,  Na Rae Oh

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes: a first active pattern extended in a first direction on a substrate; a second active pattern extended in the first direction and spaced apart from the first active pattern in a second direction on the substrate; a field insulating layer between the first active pattern and the second active pattern on the substrate; a first gate electrode on the first active pattern; a second gate electrode on the second active pattern; and a gate isolation structure separating the first gate electrode and the second gate electrode from each other on the field insulating layer, wherein a width of the gate isolation structure in the second direction varies in a downward direction from the upper isolation pattern.