公开(公告)号：US11706919B2

公开(公告)日：2023-07-18

申请号：US17038945

申请日：2020-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokcheon Baek

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A vertical memory device includes first horizontal gate electrodes disposed on a substrate and spaced apart from each other in a first direction that is substantially perpendicular to an upper surface of the substrate. Each of the first horizontal gate electrodes extends in a second direction that is substantially parallel to the upper surface of the substrate. A vertical channel extends through the first horizontal gate electrodes in the first direction. A charge storage structure is disposed between the vertical channel and each of the first horizontal gate electrodes. A first vertical gate electrode extends through the first horizontal gate electrodes in the first direction. The first vertical gate electrode is electrically insulated from the first horizontal gate electrodes. A first horizontal channel is disposed at a portion of each of the first horizontal gate electrodes adjacent to the first vertical gate electrode.

公开(公告)号：US11600632B2

公开(公告)日：2023-03-07

申请号：US16752141

申请日：2020-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jisung Cheon ,  Seokcheon Baek

IPC: H01L27/11582 ,  H01L27/1157

Abstract: A vertical memory device is provided including a first structure on a substrate. The first structure includes gate patterns spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate to form a plurality of layers. A second structure is connected to the first structure. The second structure includes pad patterns electrically connected to the gate patterns of a respective one of the layers. A channel structure passes through the gate patterns. A first contact plug passes through the second structure and electrically connects with a pad pattern of one of the layers. The first contact plug is electrically insulated from gate patterns of other layers. At least one bent portion is included at each of a sidewall of the channel structure and a sidewall of the first contact plug.

公开(公告)号：US11587940B2

公开(公告)日：2023-02-21

申请号：US16412875

申请日：2019-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon Baek ,  Geunwon Lim ,  Jaehoon Shin ,  Myungkeun Lee

IPC: H01L27/11556 ,  H01L29/792 ,  H01L27/11582

Abstract: Disclosed is a three-dimensional semiconductor memory device comprising a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, first to fourth stack structures spaced apart in a first direction on the second substrate, first and second support connectors between the second and third stack structures, third and fourth support connectors between the third and fourth stack structures, and a through dielectric pattern penetrating the first stack structure and the second substrate. A first distance between the first and second support connectors is different from a second distance between the third and fourth support connectors.

公开(公告)号：US11164886B2

公开(公告)日：2021-11-02

申请号：US16733849

申请日：2020-01-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokcheon Baek

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L23/522

Abstract: A three-dimensional semiconductor memory device including: a substrate including a cell array region and a connection region; and an electrode structure extending along a first direction from the cell array region to the connection region and including a plurality of electrodes vertically stacked on the substrate, each of the electrodes including an electrode portion on the cell array region and a pad portion on the connection region, wherein the electrodes include a first electrode located at a first level from the substrate and a second electrode located at a second level from the substrate, the second level being higher than the first level, and the pad portion of the first electrode is closer to the cell array region than the pad portion of the second electrode.

公开(公告)号：US12213310B2

公开(公告)日：2025-01-28

申请号：US17514019

申请日：2021-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokcheon Baek ,  Seungjun Lee

IPC: H10B41/27 ,  H01L25/10 ,  H01L25/18 ,  H10B43/27 ,  H01L25/065

Abstract: A semiconductor device includes a substrate having a first region and a second region, gate electrodes stacked in a first direction on the first region and each including a pad region having an upper surface exposed upwardly in the second region, channel structures penetrating the gate electrodes and extending in the first direction, separation regions penetrating the gate electrodes and extending in the second direction, contact plugs each penetrating the pad region of each of the gate electrodes and extending in the first direction, a nitride layer disposed in an external side of a lowermost first gate electrode among the gate electrodes, spaced apart from the lowermost first gate electrode, and extending horizontally, and a dummy gate electrode disposed between the lowermost first gate electrode and the nitride layer in the second direction and having a first end spaced apart from the lowermost first gate electrode.

公开(公告)号：US11756900B2

公开(公告)日：2023-09-12

申请号：US17367082

申请日：2021-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yujin Kwon ,  Seokcheon Baek ,  Younghwan Son

IPC: H01L23/00 ,  H01L23/528 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/562 ,  H01L23/528 ,  H01L24/08 ,  H01L25/18 ,  H01L2224/08146 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor device includes first and second gate electrodes stacked and spaced apart from each other in a first direction on a first region of a substrate, and extending in staircase form in a second direction on a second region of the substrate, the second gate electrodes disposed on the first gate electrodes; a first support structure penetrating the first gate electrodes on the second region, extending in the first direction, and having an upper end disposed at a level lower than a level of a lowermost second gate electrode among the second gate electrodes; a second support structure penetrating at least one of the first and second gate electrodes on the second region, extending in the first direction, and having an upper end disposed at a level higher than a level of un uppermost second gate electrode among the second gate electrodes.

公开(公告)号：US20210151462A1

公开(公告)日：2021-05-20

申请号：US17013724

申请日：2020-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon Baek

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556

Abstract: A semiconductor device includes gate electrodes stacked to be spaced apart from each other on a substrate in a first direction, extending in a second direction, and including pad regions bent in a third direction, sacrificial insulating layers extending from the gate electrodes to be stacked alternately with the interlayer insulating layers, separation regions penetrating through the gate electrodes, extending in the second direction, and spaced apart from each other to be parallel to each other, and a through-wiring region spaced apart from the separation regions to overlap the pad regions between the separation regions adjacent to each other and including contact plugs penetrating through the pad regions. The through-wiring region includes slit regions, and each of the slit regions is disposed to penetrate through the sacrificial insulating layers on one side of a respective pad region.

公开(公告)号：US10978475B2

公开(公告)日：2021-04-13

申请号：US16570106

申请日：2019-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon Baek

IPC: H01L27/00 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L23/535 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/528 ,  H01L27/1157

Abstract: A three-dimensional semiconductor memory device may include a substrate including a cell array region and a pad region, a first conductive line on the cell array region and the pad region of the substrate, a second conductive line between the first conductive line and the substrate, the second conductive line including a first portion on the cell array region and a second portion on the pad region and exposed by the first conductive line in a plan view, a first edge pattern between the substrate and the first conductive line and between the first and second portions of the second conductive line, and a first cell contact plug on the pad region of the substrate that penetrates the first conductive line and the first edge pattern.

公开(公告)号：US20190319042A1

公开(公告)日：2019-10-17

申请号：US16222059

申请日：2018-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon Baek ,  Geunwon LIM ,  Hwan LEE

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/792

Abstract: A three-dimensional semiconductor memory device includes a horizontal semiconductor layer on a peripheral logic structure, a cell electrode structure including cell gate electrodes vertically stacked on the horizontal semiconductor layer, ground selection gate electrodes provided between the cell electrode structure and the horizontal semiconductor layer and horizontally spaced apart from each other, each of the ground selection gate electrodes including first and second pads spaced apart from each other with the cell electrode structure interposed therebetween in a plan view, a first through-interconnection structure connecting the first pads of the ground selection gate electrodes to the peripheral logic structure, and a second through-interconnection structure connecting the second pads of the ground selection gate electrodes to the peripheral logic structure.

公开(公告)号：US20170103996A1

公开(公告)日：2017-04-13

申请号：US15252931

申请日：2016-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woong-Seop Lee ,  Seokcheon Baek ,  Jinhyun Shin

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11575

Abstract: A vertical NAND-type memory device includes a vertical stack of inter-gate insulating layers and gate electrodes arranged in an alternating sequence on an underlying substrate, which includes a cell array region and a contact region therein. At least one NAND-type channel structure is provided, which extends vertically through the vertical stack of inter-gate insulating layers and gate electrodes. An end sidewall of a first of the gate electrodes, which extends laterally over at least a portion of the contact region, has a vertical slope that is less steep than vertical slopes of end sidewalls of a first plurality of the gate electrodes extending between the first of the gate electrodes and the substrate.