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    Electronic device including circuit board placed adjacent to frame made of conductive material
    1.
    发明授权
    Electronic device including circuit board placed adjacent to frame made of conductive material 有权

    公开(公告)号：US12047522B2

    公开(公告)日：2024-07-23

    申请号：US17673216

    申请日：2022-02-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sanguk Kim ,  Jongdoo Kim ,  Hyoseok Na ,  Daeseung Park ,  Wanjae Ju

    IPC: H05K5/00 ,  H04M1/02

    CPC classification number: H04M1/0249 ,  H04M1/0216

    Abstract: An electronic device is provided. The electronic device includes a first mechanical element, a second mechanical element moving with respect to the first mechanical element, a frame including a first frame formed of a conductive material and coupled to the first mechanical element and a second frame formed of a conductive material and coupled to the second mechanical element, a segmentation part formed at the frame to segment each of the first frame and the second frame into a plurality of parts, and a first substrate member which includes a first part and a second part spaced apart from each other, and a first bending part for bendably connecting the first part and the second part and is disposed to move together with at least one of the first mechanical element and the second mechanical element, wherein a plurality of wires arranged at the first substrate member may be arranged not to pass through a first area which is an area of the first bending part of the first substrate member and is adjacent to the segmentation part.

    SEMICONDUCTOR PACKAGE WITH BARRIER LAYER
    2.
    发明申请
    SEMICONDUCTOR PACKAGE WITH BARRIER LAYER 有权

    公开(公告)号：US20220189881A1

    公开(公告)日：2022-06-16

    申请号：US17689108

    申请日：2022-03-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sanguk Kim

    IPC: H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

    Abstract: A packaged integrated circuit device includes a frame having a cavity therein and an inner semiconductor chip within the cavity. A lower re-distribution layer is provided, which extends adjacent lower surfaces of the frame and the inner semiconductor chip. The lower re-distribution layer has an opening therein which at least partially exposes the lower surface of the inner semiconductor chip. A lower semiconductor chip is provided, which extends adjacent the lower surface of the inner semiconductor chip, and within the opening in the lower re-distribution layer. This lower re-distribution layer includes: (i) an insulating layer covering the lower surface of the frame, (ii) a re-distribution pattern disposed on the insulating layer, and (iii) a barrier layer, which is disposed on the insulating layer and surrounds at least a portion of the lower semiconductor chip.

    SEMICONDUCTOR PACKAGE WITH BARRIER LAYER
    5.
    发明申请
    SEMICONDUCTOR PACKAGE WITH BARRIER LAYER 有权

    公开(公告)号：US20210225772A1

    公开(公告)日：2021-07-22

    申请号：US16929956

    申请日：2020-07-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sanguk Kim

    IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56

    Abstract: A packaged integrated circuit device includes a frame having a cavity therein and an inner semiconductor chip within the cavity. A lower re-distribution layer is provided, which extends adjacent lower surfaces of the frame and the inner semiconductor chip. The lower re-distribution layer has an opening therein which at least partially exposes the lower surface of the inner semiconductor chip. A lower semiconductor chip is provided, which extends adjacent the lower surface of the inner semiconductor chip, and within the opening in the lower re-distribution layer. This lower re-distribution layer includes: (i) an insulating layer covering the lower surface of the frame, (ii) a re-distribution pattern disposed on the insulating layer, and (iii) a barrier layer, which is disposed on the insulating layer and surrounds at least a portion of the lower semiconductor chip.

    Detection circuit and electronic device including same
    7.
    发明授权
    Detection circuit and electronic device including same 有权

    公开(公告)号：US12013444B2

    公开(公告)日：2024-06-18

    申请号：US17435529

    申请日：2021-08-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sanguk Kim ,  Taekho Lee

    IPC: G01R31/55 ,  G01R15/18 ,  G01R19/00 ,  G01R19/165

    CPC classification number: G01R31/55 ,  G01R15/18 ,  G01R19/0084 ,  G01R19/16566

    Abstract: Disclosed is an electronic device is provided. The electronic device includes a first substrate, a second substrate arranged to be spaced apart from the first substrate, a first cable electrically connecting a first point on the first substrate and a second point on the second substrate, and a second cable electrically connecting a third point on the first substrate and a fourth point on the second substrate. The first substrate may include a first communication circuit, a second communication circuit, a detection circuit, a voltage application unit, and a ground unit, and a second substrate may include a first antenna, a first capacitive element, a second antenna, a second capacitive element, and an isolation circuit. The isolation circuit may isolate a radio frequency (RF) signal between the first path and the second path, and electrically connect the detection circuit to the ground unit through the first cable and the second cable.

    PASSIVE DEVICE MODULE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
    9.
    发明申请
    PASSIVE DEVICE MODULE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME 有权

    公开(公告)号：US20210082890A1

    公开(公告)日：2021-03-18

    申请号：US16816555

    申请日：2020-03-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sanguk Kim

    IPC: H01L25/16 ,  H01L23/31 ,  H01L23/538 ,  H01L23/64

    Abstract: A semiconductor package including a lower redistribution layer including wiring patterns; a lower substrate on the lower redistribution layer, the lower substrate including a cavity; an application processor on the lower redistribution layer in the cavity; a cache memory chip on the application processor; a passive device module on the application processor; a plurality of first through-silicon vias penetrating the application processor to connect the lower redistribution layer to the passive device module; and lower bumps on a bottom surface of the lower redistribution layer, wherein the passive device module is adjacent to a side of the cache memory chip.

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