公开(公告)号：US11626385B2

公开(公告)日：2023-04-11

申请号：US17178327

申请日：2021-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namhoon Kim ,  Chajea Jo ,  Ohguk Kwon ,  Hyoeun Kim ,  Seunghoon Yeon

IPC: H01L25/065 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.

公开(公告)号：US11545512B2

公开(公告)日：2023-01-03

申请号：US17154890

申请日：2021-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chajea Jo ,  Ohguk Kwon ,  Hyoeun Kim ,  Seunghoon Yeon

IPC: H01L27/146 ,  H04N5/225

Abstract: An image sensor package comprises: an image sensor chip configured to convert light collected from an outside thereof into an electrical signal; a package substrate disposed under the image sensor chip the package substrate configured to process the electrical signal converted from the image sensor chip; a glass substrate disposed over the image sensor chip while being spaced apart from the image sensor chip; a seal pattern disposed between an upper surface of the package substrate and a lower surface of the glass substrate while surrounding the image sensor chip; and a protection pattern disposed on the package substrate outside the seal pattern, the protection pattern comprising a single-component material, wherein the seal pattern comprises a material different from the material of the protection pattern.

公开(公告)号：US20240055403A1

公开(公告)日：2024-02-15

申请号：US18136499

申请日：2023-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changeun Joo ,  Ohguk Kwon ,  Sunjae Kim

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/5383 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/32 ,  H01L24/16 ,  H01L24/73 ,  H01L2225/06568 ,  H01L2224/32145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/73253

Abstract: A semiconductor package may include a first redistribution substrate, a second redistribution substrate on the first redistribution substrate, a chip stack between the first redistribution substrate and the second redistribution substrate, a first molding layer on the chip stack, and a through electrode extending into the first molding layer and electrically connecting the first redistribution substrate to the second redistribution substrate. The chip stack may include a first semiconductor chip on the first redistribution substrate, the first semiconductor chip including a through via that extends therein, a chip structure including a second semiconductor chip and a second molding layer, the second semiconductor chip being on the first semiconductor chip and electrically connected to the through via, and a third semiconductor chip between the chip structure and the second redistribution substrate, and a side surface of the first semiconductor chip may be coplanar with a side surface of the chip structure.

公开(公告)号：US11735566B2

公开(公告)日：2023-08-22

申请号：US17375511

申请日：2021-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ohguk Kwon ,  Namhoon Kim ,  Hyoeun Kim ,  Sunkyoung Seo

IPC: H01L25/065 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386

Abstract: A semiconductor package including a substrate; a first semiconductor chip on the substrate; a second semiconductor chip on the first semiconductor chip; and at least one connection terminal between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip includes a first semiconductor chip body; and at least one upper pad on a top surface of the first semiconductor chip body and in contact with the at least one connection terminal, the at least one upper pad includes a recess that is downwardly recessed from a top surface thereof, and a depth of the recess is less than a thickness of the at least one upper pad.

公开(公告)号：US11710757B2

公开(公告)日：2023-07-25

申请号：US17227650

申请日：2021-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ohguk Kwon ,  Hyoeun Kim ,  Sunkyoung Seo ,  Sang-Uk Han

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L27/14634 ,  H01L23/481 ,  H01L24/08 ,  H01L24/73 ,  H01L24/89 ,  H01L27/1469 ,  H01L27/14627 ,  H01L2224/08146 ,  H01L2224/73204 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a molding layer, a silicon layer on the molding layer, a glass upwardly spaced apart from the silicon layer, and a connection dam coupled to the silicon layer and connecting the silicon layer to the glass. The silicon layer includes a silicon layer body, a silicon layer via extending vertically in the silicon layer body, and a micro-lens array on a top surface of the silicon layer body. A bottom surface of the silicon layer body contacts a top surface of the molding layer. The molding layer includes a molding layer body, a molding layer via that extends vertically in the molding layer body and has electrical connection with the silicon layer via, and a connection ball connected to a bottom surface of the molding layer via.

公开(公告)号：US11990452B2

公开(公告)日：2024-05-21

申请号：US18120587

申请日：2023-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namhoon Kim ,  Chajea Jo ,  Ohguk Kwon ,  Hyoeun Kim ,  Seunghoon Yeon

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/02 ,  H01L25/0652 ,  H01L2224/02372 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/18161

Abstract: A semiconductor package includes a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.

公开(公告)号：US11887913B2

公开(公告)日：2024-01-30

申请号：US18066487

申请日：2022-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chajea Jo ,  Ohguk Kwon ,  Namhoon Kim ,  Hyoeun Kim ,  Seunghoon Yeon

IPC: H01L23/48 ,  H01L25/065 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/562 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0652 ,  H01L2224/05008 ,  H01L2224/05025 ,  H01L2224/13026 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/351

Abstract: An integrated circuit device includes a semiconductor substrate, first through-silicon-via (TSV) structures penetrating a first region of the semiconductor substrate and spaced apart from each other by a first pitch, a first individual device between the first TSV structures and spaced apart from the first TSV structures by a distance that is greater than a first keep-off distance, and second TSV structures penetrating a second region of the semiconductor substrate and spaced apart from each other by a second pitch that is less than the first pitch. The second region of the semiconductor device does not include an individual device that is homogeneous with the first individual device and between the second TSV structures.

公开(公告)号：US11545417B2

公开(公告)日：2023-01-03

申请号：US17162418

申请日：2021-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chajea Jo ,  Ohguk Kwon ,  Namhoon Kim ,  Hyoeun Kim ,  Seunghoon Yeon

IPC: H01L23/48 ,  H01L25/065 ,  H01L21/768 ,  H01L23/00

Abstract: An integrated circuit device includes a semiconductor substrate, first through-silicon-via (TSV) structures penetrating a first region of the semiconductor substrate and spaced apart from each other by a first pitch, a first individual device between the first TSV structures and spaced apart from the first TSV structures by a distance that is greater than a first keep-off distance, and second TSV structures penetrating a second region of the semiconductor substrate and spaced apart from each other by a second pitch that is less than the first pitch. The second region of the semiconductor device does not include an individual device that is homogeneous with the first individual device and between the second TSV structures.