公开(公告)号：US20160372423A1

公开(公告)日：2016-12-22

申请号：US15156327

申请日：2016-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mi-Na CHOI ,  Young-Deuk KIM ,  Jae-Choon KIM ,  Eon-Soo JANG ,  Hee-Jung HWANG

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/49175 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2224/45099

Abstract: A package substrate may include an insulating substrate, internal circuits and a warpage-suppressing member. The insulating substrate may have a plurality of mount regions in which semiconductor chips may be mounted, and a peripheral region. The internal circuits may be arranged in the mount regions. The warpage-suppressing member is different from the semiconductor chips and may be arranged in at least one of the mount regions to suppress a warpage of the insulating substrate. Thus, warpage of the package substrate may be suppressed during a reflow process.

Abstract translation: 封装基板可以包括绝缘基板，内部电路和翘曲抑制部件。 绝缘基板可以具有可以安装半导体芯片的多个安装区域和周边区域。 内部电路可以布置在安装区域中。 翘曲抑制部件与半导体芯片不同，并且可以布置在至少一个安装区域中，以抑制绝缘基板的翘曲。 因此，可以在回流工艺期间抑制封装衬底的翘曲。

公开(公告)号：US20250149456A1

公开(公告)日：2025-05-08

申请号：US18670911

申请日：2024-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Ja KIM ,  Sun Won KANG ,  Mi-Na CHOI

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package includes a substrate having a vent hole defined therein. Semiconductor chips are mounted on an upper surface of the substrate. Chip connection terminals are disposed between the substrate and the semiconductor chips. Substrate connection terminals are disposed on a lower surface of the substrate. A plated layer includes a vertical heat-dissipation layer on an inner wall of the vent hole, a first heat-dissipation layer on the upper surface of the substrate and connected to at least one of the chip connection terminals and a second heat-dissipation layer on the lower surface of the substrate and connected to at least one of the substrate connection terminals. An encapsulant covers the upper surface of the substrate, the chip connection terminals, and the semiconductor chips, and fills a space between the semiconductor chips and the substrate. The encapsulant is on the plated layer and fills the vent hole.

公开(公告)号：US20140184312A1

公开(公告)日：2014-07-03

申请号：US14196602

申请日：2014-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Choon KIM ,  Eunseok CHO ,  Mi-Na CHOI ,  Kyoungsei CHOI ,  Heejung HWANG ,  Seran BAE

IPC: G05F1/46

CPC classification number: G05F1/463 ,  H01L23/34 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49822 ,  H01L25/16 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/00

Abstract: An example embodiment relates to a semiconductor device including a semiconductor package in which a semiconductor chip is mounted on the package substrate. The semiconductor package may include a temperature measurement device and a temperature control circuit. The temperature measurement device may measure a temperature of the semiconductor package. The temperature control circuit may change an operation speed of the semiconductor package on the basis of the temperature of the semiconductor package measured by the temperature measurement device.

Abstract translation: 示例性实施例涉及一种包括半导体封装的半导体器件，其中半导体芯片安装在封装衬底上。 半导体封装可以包括温度测量装置和温度控制电路。 温度测量装置可以测量半导体封装的温度。 温度控制电路可以基于由温度测量装置测量的半导体封装的温度来改变半导体封装的操作速度。

公开(公告)号：US20140239300A1

公开(公告)日：2014-08-28

申请号：US14068091

申请日：2013-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mi-Na CHOI ,  Ji-Chul KIM ,  Se-Ran BAE ,  Eun-Seok CHO ,  Hee-Jung HWANG

IPC: H01L21/66

CPC classification number: H01L23/345 ,  G01R31/2875 ,  H01L22/34 ,  H01L23/34 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: Semiconductor test devices and methods for fabricating the same may be provided. The semiconductor test device may include a first thermal test flip chip cell including a first heater and a first sensor, and a test substrate formed under the first thermal test flip chip cell. The first thermal test flip chip cell may include a plurality of first bumps arranged on a bottom surface of the first thermal test flip chip cell and be configured to be electrically connected to the first heater and the first sensor. The test substrate may include a first ball array arranged on a bottom surface of the test substrate in a first direction and be configured to be electrically connected to the plurality of first bumps, which are electrically connected to the first heater and the first sensor.

Abstract translation: 可以提供半导体测试装置及其制造方法。 半导体测试装置可以包括第一热测试倒装芯片单元，其包括第一加热器和第一传感器，以及形成在第一热测试倒装芯片单元下的测试基板。 第一热测试倒装芯片单元可以包括布置在第一热测试倒装芯片单元的底表面上的多个第一凸块，并且被配置为电连接到第一加热器和第一传感器。 测试基板可以包括在第一方向上布置在测试基板的底表面上的第一球阵列，并且被配置为电连接到电连接到第一加热器和第一传感器的多个第一凸块。