公开(公告)号：US20190303226A1

公开(公告)日：2019-10-03

申请号：US16218720

申请日：2018-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINSU KIM ,  JISEOK KANG ,  MINSOO KIM ,  BYUNGJIK KIM ,  WONJAE SHIN ,  DONGHOON LEE ,  YEONHWA LEE ,  HO-YOUNG LEE ,  YOUJIN JANG ,  INSU CHOI

IPC: G06F11/07 ,  G06F12/0804 ,  G06F12/02

Abstract: A semiconductor memory module may include a random access memory, a nonvolatile memory, a buffer memory, and a controller configured to execute a reading operation on the buffer memory in response to an activation of a control signal. The controller may be further configured to execute a flush operation of storing first data, which are stored in the random access memory, in the nonvolatile memory, according to a result of the reading operation.

公开(公告)号：US20230230946A1

公开(公告)日：2023-07-20

申请号：US17939127

申请日：2022-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongyo KIM ,  UN-BYOUNG KANG ,  MINSOO KIM ,  SANG-SICK PARK ,  Seungyoon JUNG

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/08 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/81203 ,  H01L24/81 ,  H01L2924/3511 ,  H01L2924/182 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/1703 ,  H01L2224/17055 ,  H01L2224/17104 ,  H01L2224/17179 ,  H01L2224/17132 ,  H01L2224/16012 ,  H01L2224/16055 ,  H01L2224/16059 ,  H01L2224/16104 ,  H01L2224/0801 ,  H01L2224/08056 ,  H01L2224/08055 ,  H01L2224/0903 ,  H01L2224/09179 ,  H01L2224/09132 ,  H01L2224/73204

Abstract: A semiconductor package comprises a first die having a central region and a peripheral region that surrounds the central region; a plurality of through electrodes that penetrate the first die; a plurality of first pads at a top surface of the first die and coupled to the through electrodes; a second die on the first die; a plurality of second pads at a bottom surface of the second die, the bottom surface of the second die facing the top surface of the first die; a plurality of connection terminals that connect the first pads to the second pads; and a dielectric layer that fills a space between the first die and the second die and surrounds the connection terminals. A first width of each of the first pads in the central region may be greater than a second width of each of the first pads in the peripheral region. Each of the connection terminals may include a convex portion at a lateral surface thereof, which protrudes beyond a lateral surface of a respective first pad and a lateral surface of a respective second pad. The convex portion may protrude in a direction away from a center of the first die. Protruding distances of the convex portions may increase in a direction from the center of the first die toward an outside of the first die.

公开(公告)号：US20250070072A1

公开(公告)日：2025-02-27

申请号：US18640576

申请日：2024-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongyo KIM ,  MINSOO KIM ,  SANG-SICK PARK

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor die, a first under-fill layer on an upper surface of the first semiconductor die, a second under-fill layer on the first under-fill layer, a second semiconductor die provided on the second under-fill layer, and a mold layer on side surfaces of the second semiconductor die, the second under-fill layer, and the upper surface of the first semiconductor die. The first semiconductor die includes a first substrate, a first redistribution pattern on the first substrate, a first redistribution dielectric layer provided on the first redistribution pattern, and a first dam on the first redistribution dielectric layer and along an edge of the first substrate, and the first under-fill layer contacts a side surface of the first dam.