公开(公告)号：US08947950B2

公开(公告)日：2015-02-03

申请号：US13770150

申请日：2013-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Suk Chae ,  Satoru Yamada

IPC: G11C7/00 ,  H01L29/78 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: H01L29/7816 ,  G11C7/00 ,  G11C11/4094 ,  G11C11/4096 ,  G11C2207/005

Abstract: A semiconductor memory device includes a bit line connected to a memory cell; an input/output line configured to input a data signal to the memory cell during a writing operation and to output a data signal stored in the memory cell during a reading operation; and a column select transistor including a first source/drain connected to the bit line and a second source/drain connected to the input/output line, wherein a resistance of the first source/drain is smaller than a resistance of the second source/drain.

Abstract translation: 半导体存储器件包括连接到存储器单元的位线; 输入/输出线，被配置为在写入操作期间将数据信号输入到存储器单元，并且在读取操作期间输出存储在存储单元中的数据信号; 以及列选择晶体管，其包括连接到所述位线的第一源极/漏极和连接到所述输入/输出线的第二源极/漏极，其中所述第一源极/漏极的电阻小于所述第二源极/漏极的电阻 。

公开(公告)号：US11778810B2

公开(公告)日：2023-10-03

申请号：US17332307

申请日：2021-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin A Kim ,  Ho-In Ryu ,  Kyo-Suk Chae ,  Joon Yong Choe

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/315 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor device may include a substrate including trenches and contact recesses having a curved surface profile, conductive patterns in the trenches, buried contacts including first portions filling the contact recesses and second portions on the first portions, and spacer structures including first and second spacers. The second portions may have a pillar shape and a smaller width than top surfaces of the first portions. The buried contacts may be spaced apart from the conductive patterns by the spacer structures. The first spacers may be on the first portions of the buried contacts at outermost parts of the spacer structures. The first spacers may extend along the second portions of the buried contacts and contact the buried contacts. The second spacers may extend along the side surfaces of the conductive patterns and the trenches. The second spacers may contact the conductive patterns. The first spacers may include silicon oxide.

公开(公告)号：US20240121945A1

公开(公告)日：2024-04-11

申请号：US18347927

申请日：2023-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Seong Lee ,  Tai Uk Rim ,  Ji Hun Kim ,  Kyo-Suk Chae

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315

Abstract: A semiconductor memory device comprises a substrate including a first source/drain region and a second source/drain region, a trench between the first source/drain region and the second source/drain region and formed in the substrate, a cell gate insulating layer on sidewalls and a bottom surface of the trench, a cell gate electrode on the cell gate insulating layer, a work function control pattern on the cell gate electrode, including N-type impurities and a cell gate capping pattern on the work function control pattern. The work function control pattern includes a semiconductor material. The work function control pattern includes a first region and a second region between the first region and the cell gate electrode. A concentration of the N-type impurities in the first region is greater than a concentration of the N-type impurities in the second region.

公开(公告)号：US20230085456A1

公开(公告)日：2023-03-16

申请号：US17859472

申请日：2022-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Suk Chae ,  Dongsik Kong ,  Youngwook Park ,  Jihoon Kim ,  Myung-Hyun Baek ,  Ju Hyung We ,  Jun-Bum Lee

IPC: H01L29/423 ,  H01L21/306 ,  H01L21/02 ,  H01L21/762 ,  H01L21/768

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate having a groove therein extending in a first direction, a gate insulating layer in the groove, a first conductive pattern in the groove and on the gate insulating layer, and a word line capping pattern in the groove and on the first conductive pattern. The first conductive pattern may include a first material and may include a first conductive portion adjacent to the word line capping pattern and a second conductive portion adjacent to a bottom end of the groove. A largest dimension of a grain of the first material of the first conductive portion may be equal to or larger than that of the first material of the second conductive portion.

公开(公告)号：US10424649B2

公开(公告)日：2019-09-24

申请号：US16026097

申请日：2018-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joon-Seok Moon ,  Dong Sik Kong ,  Sung Won Yoo ,  Hee Sun Joo ,  Kyo-Suk Chae

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/78 ,  H01L27/108

Abstract: A semiconductor device includes a substrate, device isolation film defining an active region of the substrate in which a gate trench extends, a gate insulating film disposed along sides and a bottom of the gate trench, a gate electrode disposed on the gate insulating film in the gate trench and having a first portion, a second portion on the first portion, and a third portion on the second portion, a first barrier film pattern interposed between the first portion of the gate electrode and the gate insulating film, a second barrier film pattern interposed between the second portion of the gate electrode and the gate insulating film, and a third barrier film pattern interposed between the third portion of the gate electrode and the gate insulating film. The work function of the first barrier film pattern is greater than the work function of the second barrier film pattern and less than the work function of the third barrier film pattern.

公开(公告)号：US10431680B2

公开(公告)日：2019-10-01

申请号：US15391888

申请日：2016-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungsam Lee ,  Junsoo Kim ,  Hyoshin Ahn ,  Satoru Yamada ,  Joohyun Jeon ,  MoonYoung Jeong ,  Chunhyung Chung ,  Min Hee Cho ,  Kyo-Suk Chae ,  Eunae Choi

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/04

Abstract: A semiconductor device including a semiconductor substrate including a trench, the semiconductor substrate having a crystal structure; and an insulating layer covering an inner sidewall of the trench, wherein the inner sidewall of the trench has at least one plane included in a {320} family of planes of the crystal structure or at least one plane similar to the {320} family of planes.

公开(公告)号：US20130279275A1

公开(公告)日：2013-10-24

申请号：US13770150

申请日：2013-02-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyo-Suk Chae ,  Satoru Yamada

IPC: H01L29/78 ,  G11C7/00

CPC classification number: H01L29/7816 ,  G11C7/00 ,  G11C11/4094 ,  G11C11/4096 ,  G11C2207/005

Abstract: A semiconductor memory device includes a bit line connected to a memory cell; an input/output line configured to input a data signal to the memory cell during a writing operation and to output a data signal stored in the memory cell during a reading operation; and a column select transistor including a first source/drain connected to the bit line and a second source/drain connected to the input/output line, wherein a resistance of the first source/drain is smaller than a resistance of the second source/drain.

Abstract translation: 半导体存储器件包括连接到存储器单元的位线; 输入/输出线，被配置为在写入操作期间将数据信号输入到存储器单元，并且在读取操作期间输出存储在存储单元中的数据信号; 以及列选择晶体管，其包括连接到所述位线的第一源极/漏极和连接到所述输入/输出线的第二源极/漏极，其中所述第一源极/漏极的电阻小于所述第二源极/漏极的电阻 。