公开(公告)号：US20250087570A1

公开(公告)日：2025-03-13

申请号：US18626700

申请日：2024-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNSOO CHUNG ,  KWANG-SOO KIM ,  CHI WOO LEE

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package includes a redistribution layer structure, a first sub-package positioned on the redistribution layer structure, a second sub-package positioned on the first sub-package, and a first encapsulant positioned on the first sub-package and encapsulating the second sub-package. The first sub-package includes a first semiconductor chip including a first chip through via and a dielectric through via electrically connected to the redistribution layer structure. The second sub-package includes a second semiconductor chip including a plurality of second chip through vias, each second chip through via electrically connected to one of the first chip through via and the dielectric through via, a third semiconductor chip positioned on the second semiconductor chip, and a fourth semiconductor chip positioned on the third semiconductor chip. Each of the second to fourth semiconductor chips is exposed at a side surface of the second sub-package and covered with the first encapsulant.

公开(公告)号：US20200066742A1

公开(公告)日：2020-02-27

申请号：US16398442

申请日：2019-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNHYOUNG KIM ,  KWANG-SOO KIM ,  GEUNWON LIM ,  JISUNG CHEON

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device may include a first stack block including first stacks arranged in a first direction on a substrate, a second stack block including second stacks arranged in the first direction on the substrate, and a separation structure provided on the substrate between the first stack block and the second stack block. The separation structure may include first mold layers and second mold layers, which are stacked in a vertical direction perpendicular to a top surface of the substrate.

公开(公告)号：US20190157297A1

公开(公告)日：2019-05-23

申请号：US16261694

申请日：2019-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KWANG-SOO KIM ,  TAE-SEOK JANG

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/522

Abstract: A vertical semiconductor device includes odd and even cell blocks, and odd and even block pad structures. Each of the odd cell blocks includes first conductive line structures including conductive lines and insulation layers alternatively stacked in a first direction. Each of the even cell blocks includes second conductive line structures having substantially the same shape as the first conductive line structures. The odd block pad structure is connected to first edge portions of the first conductive line structures. The even block pad structure is connected to second edge portions, opposite the first edge portions, of the second conductive line structures. Each of the odd cell blocks and the even cell blocks has a first width in a third direction. Each of the odd and even block pad structures is formed on a region of a substrate having a second width greater than the first width in the third direction.

公开(公告)号：US20250096175A1

公开(公告)日：2025-03-20

申请号：US18794640

申请日：2024-08-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YISEUL HAN ,  KWANG-SOO KIM ,  JAESUN KIM

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package includes a first redistribution layer structure, a first set of semiconductor dies on the first redistribution layer structure, a plurality of connection members on the first redistribution layer structure and around the first set of semiconductor dies, a molding material on the first redistribution layer structure, the molding material covering the first set of semiconductor dies and at least partially surrounding the plurality of connection members, a second redistribution layer structure on the molding material, a second set of semiconductor dies on the second redistribution layer structure, and a dummy structure on the second redistribution layer structure and between a first semiconductor die of the second set of semiconductor dies and a second semiconductor die of the second set of semiconductor dies.

公开(公告)号：US20170108329A1

公开(公告)日：2017-04-20

申请号：US15206613

申请日：2016-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： KWANG-SOO KIM ,  Harutaka SEKIYA ,  Kwang-jun YOON ,  Sung-won PARK ,  Young-duk KIM ,  Heon-ju SHIN ,  Byeong-hwan JEON

IPC: G01B11/00 ,  G01N21/01 ,  G01N21/956 ,  H01L21/68 ,  G01N21/95

CPC classification number: G01B11/002 ,  G01N21/9501 ,  G01N21/956 ,  G01N2201/121 ,  H01L21/681

Abstract: An automatic focus control apparatus includes a light detector, which receives light reflected by a surface of a wafer and generates a light reception signal based on the received signal, a controller, which generates a driving signal, the driving signal being one of a first signal and a second signal, the driving signal indicating whether to perform automatic focus control based on the light reception signal, a focus error corrector, which generates a focus error correction signal based on the driving signal, and a stage driver, which displaces a wafer stage supporting the wafer by adjusting the z-axis position of the wafer stage based on the focus error correcting signal if the driving signal is the first signal, and maintains the z-axis position of the wafer stage based on the focus error correction signal if the driving signal is the second signal.

公开(公告)号：US20250054913A1

公开(公告)日：2025-02-13

申请号：US18581483

申请日：2024-02-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNSOO CHUNG ,  KWANG-SOO KIM ,  WON-YOUNG KIM

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor device includes first to third semiconductor chips consecutively stacked. The first semiconductor chip comprises a first semiconductor substrate. A circuit layer is on a top surface of the first semiconductor substrate. First pads are on a top surface of the circuit layer. The first pads are electrically connected to the circuit layer. The second semiconductor chip comprises a second semiconductor substrate. Passive devices are in the second semiconductor substrate. Second pads are on a bottom surface of the second semiconductor substrate. The second pads are electrically connected to the passive devices. Third pads are on a top surface of the second semiconductor substrate. The third semiconductor chip comprises fourth pads on a bottom surface of the third semiconductor chip. The first pads and the second pads are directly connected to each other. The third pads and the fourth pads are directly connected to each other.

公开(公告)号：US20180182775A1

公开(公告)日：2018-06-28

申请号：US15636729

申请日：2017-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KWANG-SOO KIM ,  TAE-SEOK JANG

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A vertical semiconductor device includes odd and even cell blocks, and odd and even block pad structures. Each of the odd cell blocks includes first conductive line structures including conductive lines and insulation layers alternatively stacked in a first direction. Each of the even cell blocks includes second conductive line structures having substantially the same shape as the first conductive line structures. The odd block pad structure is connected to first edge portions of the first conductive line structures. The even block pad structure is connected to second edge portions, opposite the first edge portions, of the second conductive line structures. Each of the odd cell blocks and the even cell blocks has a first width in a third direction. Each of the odd and even block pad structures is formed on a region of a substrate having a second width greater than the first width in the third direction.

公开(公告)号：US20250142834A1

公开(公告)日：2025-05-01

申请号：US18732268

申请日：2024-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suseong Noh ,  Ilho Myeong ,  KWANG-SOO KIM

IPC: H10B51/30 ,  H10B51/20

Abstract: A semiconductor device includes: a substrate; a gate stacking structure that includes interlayer insulating layers and gate electrodes that are alternately stacked on the substrate; a channel structure that penetrates the gate stacking structure and extends in a first direction, and includes a channel layer connected to the substrate and a ferroelectric layer that surrounds the channel layer; a charge inflow pattern disposed on a lateral side of the ferroelectric layer and spaced apart in the first direction; and an insulation pattern disposed between the charge inflow pattern and the gate electrodes and that surrounds an exterior side, a lower side, and an upper side of the charge inflow pattern.

公开(公告)号：US20250096215A1

公开(公告)日：2025-03-20

申请号：US18626787

申请日：2024-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNSOO CHUNG ,  KWANG-SOO KIM ,  CHI WOO LEE

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498

Abstract: A semiconductor package includes a redistribution structure, a semiconductor die on the redistribution structure, one or more memory stacking structures disposed on the redistribution structure, wherein the one or more memory stacking structures and the semiconductor die are arranged side by side on the redistribution structure, an optical engine disposed on the redistribution structure, wherein the optical engine and the semiconductor die are arranged side by side on the redistribution structure, and a heat dissipation structure on the semiconductor die, the one or more memory stacking structures, and the optical engine, wherein levels of upper surfaces of the semiconductor die, the one or more memory stacking structures, and the optical engine are the same.

公开(公告)号：US20180102316A1

公开(公告)日：2018-04-12

申请号：US15831498

申请日：2017-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KWANG-SOO KIM

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/115

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/115 ,  H01L27/11582 ,  H01L28/00

Abstract: An integrated circuit (IC) device includes: a channel region that extends on the substrate to penetrate a plurality of word lines; a bit line contact pad that contacts an upper surface of the channel region; a bit line that contacts the bit line contact pad and extends on the bit line contact pad in a direction parallel to the main surface of the substrate; a common source line that partially fills a word line cut region and has a height lower than that of the channel region; and a common source via contact that contacts an upper surface of the common source line in the word line cut region.