公开(公告)号：US20230110190A1

公开(公告)日：2023-04-13

申请号：US17938684

申请日：2022-10-07

Applicant: Samsung Electronics Co., Ltd

Inventor： JINYOUNG PARK ,  Jungpyo HONG ,  Yangdoo KIM ,  Yonghwan KIM ,  Sangwuk PARK

IPC: H01L21/033 ,  H01L21/308 ,  H01L21/027

Abstract: Methods of forming a semiconductor device may include: providing a substrate on which a layer is formed; forming a lower hard-mask layer, which includes silicon, on the layer; forming an upper hard-mask pattern, which includes oxide, on the lower hard-mask layer; forming a lower hard-mask pattern by etching the lower hard-mask layer using the upper hard-mask pattern as an etch mask and using an etching gas that includes a metal-chloride-based first gas and a nitride-based second gas; and forming a plurality of contact holes in the layer by etching the material layer using the lower hard-mask pattern as an etch mask.

公开(公告)号：US20230200055A1

公开(公告)日：2023-06-22

申请号：US17874691

申请日：2022-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghwan KIM ,  Yangdoo KIM ,  Sangwuk PARK ,  Minkyu SUH ,  Sangho LEE ,  Jungpyo HONG

IPC: H01L27/108 ,  H01L27/12 ,  H01L27/13

CPC classification number: H01L27/10817 ,  H01L27/1203 ,  H01L27/13 ,  H01L27/10852 ,  H01L27/10823

Abstract: A semiconductor device including a substrate; storage node contacts on the substrate; lower electrode structures on the storage node contacts; a supporter structure on an external side surface of the lower electrode structures and connecting adjacent lower electrode structures to each other; a dielectric layer on the lower electrode structures and the supporter structure; and an upper electrode structure on the dielectric layer, wherein the lower electrode structures each include a pillar portion in contact with the storage node contacts; and a cylinder portion on the pillar portion, the pillar portion includes a first lower electrode layer having a cylindrical shape and having a lower surface and a side surface; and a first portion covering at least an internal wall of the first lower electrode layer, and the cylinder portion includes a second portion extending from the first portion and covering an upper end of the first lower electrode layer.

公开(公告)号：US20210035830A1

公开(公告)日：2021-02-04

申请号：US16821415

申请日：2020-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwangnam KIM ,  Nohsung KWAK ,  Sungyeon KIM ,  Hyungjun KIM ,  Haejoong PARK ,  Jongwoo SUN ,  Sangrok OH ,  Ilyoung HAN ,  Jungpyo HONG

IPC: H01L21/67 ,  H01L21/687 ,  H01L21/673 ,  H01L21/677

Abstract: A semiconductor manufacturing apparatus including at least one load module including a load port on which a substrate container is located, a plurality of substrates being mountable on the substrate container; at least one loadlock module including a loadlock chamber directly connected to the substrate container, the loadlock chamber interchangeably having atmospheric pressure and vacuum pressure, a first transfer robot within the loadlock chamber, and a substrate stage within the loadlock chamber, the plurality of substrates being mountable on the substrate stage; a transfer module including a transfer chamber connected to the loadlock chamber, a second transfer robot within the transfer chamber, and a substrate aligner within the transfer chamber; and at least one process module including at least one process chamber connected to the transfer module.

公开(公告)号：US20230209813A1

公开(公告)日：2023-06-29

申请号：US17961688

申请日：2022-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yuna LEE ,  Sangwuk PARK ,  Hyunchul YOON ,  Minji LEE ,  Jungpyo HONG

IPC: H01L27/108 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/10888 ,  H01L27/10885 ,  H01L23/5283 ,  H01L23/5226 ,  H01L27/10823 ,  H01L27/10897 ,  H01L27/10876 ,  H01L27/10894

Abstract: A method of fabricating a semiconductor device includes forming interconnection structures on a lower structure. An insulating layer is formed between the interconnection structures. The insulating layer is patterned to form insulating patterns. An insulating fence is formed between the insulating patterns. A first protective pattern is formed on the insulating fence. The insulating patterns are etched after the forming of the first protective pattern to form contact holes. Contact plugs are formed in the contact holes.

公开(公告)号：US20210027993A1

公开(公告)日：2021-01-28

申请号：US16905018

申请日：2020-06-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungyeon KIM ,  Jungpyo HONG ,  Kwangnam KIM ,  Hyungjun KIM ,  Jongwoo SUN

IPC: H01J37/32 ,  H01L21/67

Abstract: A substrate treating apparatus, including a process chamber having a bottom portion configured to secure a substrate while a substrate treating process is performed on the substrate; and a dielectric window arranged at an upper portion of the process chamber to define a process space, and including: an insulative body, an antenna disposed on an upper surface of the insulative body, a protection layer disposed on a lower surface of the insulative body, and an etch resistor protruding from at least a portion of the protection layer toward the process space, wherein, based on power being applied to the antenna, a plasma is generated in the process space, and wherein the insulative body is protected from the plasma by the protection layer and the etch resistor.

公开(公告)号：US20250169057A1

公开(公告)日：2025-05-22

申请号：US18745013

申请日：2024-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dokeun LEE ,  Yangdoo KIM ,  Sang Wuk PARK ,  Minkyu SUH ,  Geonyeop LEE ,  Jihye LEE ,  Jungpyo HONG

IPC: H10B12/00

Abstract: A semiconductor memory device includes a conductive pattern on a substrate, a lower electrode connected to the conductive pattern and including first and second portions, one or more electrode side wall supports supporting the lower electrode and contacting a side wall of the lower electrode, an electrode capping support disposed on the lower electrode and contacting an upper face of the lower electrode, a capacitor dielectric film on the lower electrode, the electrode side wall supports, and the electrode capping support, and an upper electrode on the capacitor dielectric film. The first portion of the lower electrode has an increasing width in the first d in a second direction increases as it goes away from the conductive pattern, and a slope of the side wall of the first portion of the lower electrode is different from a slope of the side wall of the second portion of the lower electrode.

公开(公告)号：US20240074163A1

公开(公告)日：2024-02-29

申请号：US18365397

申请日：2023-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangdoo KIM ,  Sangwuk PARK ,  Minkyu SUH ,  Geonyeop LEE ,  Dokeun LEE ,  Jungpyo HONG

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/315 ,  H10B12/485

Abstract: An integrated circuit device includes a substrate having a plurality of active regions defined therein, a first word line structure including a first word line, a first gate dielectric film surrounding the first word line, and an oxide semiconductor channel layer surrounding the first gate dielectric film, the first word line structure being buried in the substrate, and crossing a first active region of the plurality of active regions, a second word line structure including a second word line and a second gate dielectric film surrounding the second word line, the second word line structure being buried in the substrate and separated from the first word line structure, and crossing the first active region, a direct contact partially passing through the first active region and the first word line structure and contacting the oxide semiconductor channel layer, and a bit line contacting the direct contact.

公开(公告)号：US20230320061A1

公开(公告)日：2023-10-05

申请号：US17979069

申请日：2022-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minkyu SUH ,  Yangdoo KIM ,  Yonghwan KIM ,  Sangwuk PARK ,  Geonyeop LEE ,  Dokeun LEE ,  Jungpyo HONG

IPC: H01L27/108

CPC classification number: H01L27/1085

Abstract: A method of manufacturing an integrated circuit device includes forming a mold structure, which has a mold layer and a support layer sequentially stacked, on a substrate, forming a vertical hole through the mold structure in a vertical direction and a bowing space extending outward from the vertical hole in a horizontal direction in a first vertical level area, exposing the vertical hole and the bowing space to a preprocessing atmosphere to make the support layer have a first surface state and the mold layer have a second surface state different from the first surface state, forming a bowing complementary pattern filling the bowing space by a selective deposition process using the difference between the first surface state and the second surface state, and forming a lower electrode in the vertical hole and in contact with the mold layer, the support layer, and the bowing complementary pattern.