公开(公告)号：US20250169059A1

公开(公告)日：2025-05-22

申请号：US18815929

申请日：2024-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangdoo KIM ,  Sangwuk PARK ,  Minkyu SUH ,  Geonyeop LEE ,  Dokeun LEE ,  Jihye LEE

IPC: H10B12/00

Abstract: A semiconductor device includes a lower structure including conductive regions; a capacitor including first electrode structures electrically connected to the conductive regions of the lower structure, a dielectric layer covering the first electrode structures, and a second electrode structure on the dielectric layer; and an upper support pattern in contact with the first electrode structures, wherein each of the first electrode structures includes a first electrode region extending vertically; and a second electrode region extending upwardly from the first electrode region and having a side surface not vertically aligned with a side surface of the first electrode region, and wherein the upper support pattern includes a first layer covering upper surfaces of the second electrode regions of the first electrode structures and connected to each other; and a second layer on the first layer and including a material different from a material of the first layer.

公开(公告)号：US20250169057A1

公开(公告)日：2025-05-22

申请号：US18745013

申请日：2024-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dokeun LEE ,  Yangdoo KIM ,  Sang Wuk PARK ,  Minkyu SUH ,  Geonyeop LEE ,  Jihye LEE ,  Jungpyo HONG

IPC: H10B12/00

Abstract: A semiconductor memory device includes a conductive pattern on a substrate, a lower electrode connected to the conductive pattern and including first and second portions, one or more electrode side wall supports supporting the lower electrode and contacting a side wall of the lower electrode, an electrode capping support disposed on the lower electrode and contacting an upper face of the lower electrode, a capacitor dielectric film on the lower electrode, the electrode side wall supports, and the electrode capping support, and an upper electrode on the capacitor dielectric film. The first portion of the lower electrode has an increasing width in the first d in a second direction increases as it goes away from the conductive pattern, and a slope of the side wall of the first portion of the lower electrode is different from a slope of the side wall of the second portion of the lower electrode.

公开(公告)号：US20240074163A1

公开(公告)日：2024-02-29

申请号：US18365397

申请日：2023-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangdoo KIM ,  Sangwuk PARK ,  Minkyu SUH ,  Geonyeop LEE ,  Dokeun LEE ,  Jungpyo HONG

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/315 ,  H10B12/485

Abstract: An integrated circuit device includes a substrate having a plurality of active regions defined therein, a first word line structure including a first word line, a first gate dielectric film surrounding the first word line, and an oxide semiconductor channel layer surrounding the first gate dielectric film, the first word line structure being buried in the substrate, and crossing a first active region of the plurality of active regions, a second word line structure including a second word line and a second gate dielectric film surrounding the second word line, the second word line structure being buried in the substrate and separated from the first word line structure, and crossing the first active region, a direct contact partially passing through the first active region and the first word line structure and contacting the oxide semiconductor channel layer, and a bit line contacting the direct contact.

公开(公告)号：US20230320061A1

公开(公告)日：2023-10-05

申请号：US17979069

申请日：2022-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minkyu SUH ,  Yangdoo KIM ,  Yonghwan KIM ,  Sangwuk PARK ,  Geonyeop LEE ,  Dokeun LEE ,  Jungpyo HONG

IPC: H01L27/108

CPC classification number: H01L27/1085

Abstract: A method of manufacturing an integrated circuit device includes forming a mold structure, which has a mold layer and a support layer sequentially stacked, on a substrate, forming a vertical hole through the mold structure in a vertical direction and a bowing space extending outward from the vertical hole in a horizontal direction in a first vertical level area, exposing the vertical hole and the bowing space to a preprocessing atmosphere to make the support layer have a first surface state and the mold layer have a second surface state different from the first surface state, forming a bowing complementary pattern filling the bowing space by a selective deposition process using the difference between the first surface state and the second surface state, and forming a lower electrode in the vertical hole and in contact with the mold layer, the support layer, and the bowing complementary pattern.