公开(公告)号：US20230086174A1

公开(公告)日：2023-03-23

申请号：US17852658

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Mo PARK ,  Yeon Ho PARK ,  Eun Sil PARK ,  Jin Seok LEE ,  Wang Seop LIM ,  Kyu Bong CHOI

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/775 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/66

Abstract: A semiconductor device includes first and second sheet patterns spaced apart from each other on a first region of the substrate, a first gate electrode extending between the first and second sheet patterns, third and fourth sheet patterns spaced apart from each other on a second region of the substrate, and a second gate electrode extending between the third and fourth sheet patterns. The first gate electrode includes a first work function controlling film, which is between the first and second sheet patterns, and a first filling conductive film on the first work function controlling film. The second gate electrode includes a second work function controlling film, which is between the third and fourth sheet patterns, and a second filling conductive film on the second work function controlling film. A distance between the third and fourth sheet patterns is greater than a distance between the first and second sheet patterns.

公开(公告)号：US20200058652A1

公开(公告)日：2020-02-20

申请号：US16290222

申请日：2019-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Mo PARK ,  Ju Youn KIM ,  Hyung Joo NA ,  Sang Min YOO ,  Eui Chul HWANG

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238

Abstract: Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include a substrate including first and second regions, first active fins extending in a first direction on the first region, second active fins extending parallel to the first active fins on the second region, and single diffusion break regions between two first active fins. Single diffusion break regions may be spaced apart from each other in the first direction. The semiconductor devices may also include a lower diffusion break region between two second active fins and extending in a second direction that is different from the first direction and upper diffusion break regions on the lower diffusion break region. The upper diffusion break regions may be spaced apart from each other in the first direction, and each of the upper diffusion break regions may overlap the lower diffusion break region.

公开(公告)号：US20240234558A9

公开(公告)日：2024-07-11

申请号：US18201878

申请日：2023-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongmin SHIN ,  Wook Hyun KWON ,  Su-Hyeon KIM ,  Jun Mo PARK ,  Kyu Bong CHOI

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/775 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392

Abstract: A semiconductor device includes a first active pattern including a first lower pattern and first sheet patterns; a second active pattern including a second lower pattern and second sheet patterns, a height of the second lower pattern being smaller than a height of the first lower pattern; a first gate structure on the first lower pattern; a second gate structure on the second lower pattern; a first source/drain pattern on the first lower pattern and connected to the first sheet patterns; and a second source/drain pattern on the second lower pattern and connected to the second sheet patterns, wherein a width of an upper surface of the first lower pattern is different from a width of an upper surface of the second lower pattern, and wherein a number of first sheet patterns is different from a number of second sheet patterns.

公开(公告)号：US20230040132A1

公开(公告)日：2023-02-09

申请号：US17741711

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Mo PARK ,  Kyu Bong CHOI ,  Yeon Ho PARK ,  Eun Sil PARK ,  Jin Seok LEE ,  Wang Seop LIM ,  Kyung In CHOI

IPC: H01L21/02 ,  H01L21/8234 ,  H01L21/768

Abstract: A method of manufacturing a semiconductor device includes: forming first to third preliminary active patterns on a substrate to have different intervals therebetween, forming first and second field insulating layers between the first and second preliminary active patterns and between the second and third preliminary active patterns, respectively, and forming first to third gate electrodes respectively on first to third active patterns formed based on the first to third preliminary active patterns, separated by first and second gate isolation structures.

公开(公告)号：US20210118885A1

公开(公告)日：2021-04-22

申请号：US17126166

申请日：2020-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Mo PARK ,  Ju Youn KIM ,  Hyung Joo NA ,  Sang Min YOO ,  Eui Chul HWANG

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

Abstract: Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include a substrate including first and second regions, first active fins extending in a first direction on the first region, second active fins extending parallel to the first active fins on the second region, and single diffusion break regions between two first active fins. Single diffusion break regions may be spaced apart from each other in the first direction. The semiconductor devices may also include a lower diffusion break region between two second active fins and extending in a second direction that is different from the first direction and upper diffusion break regions on the lower diffusion break region. The upper diffusion break regions may be spaced apart from each other in the first direction, and each of the upper diffusion break regions may overlap the lower diffusion break region.

公开(公告)号：US20240136430A1

公开(公告)日：2024-04-25

申请号：US18201878

申请日：2023-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongmin SHIN ,  Wook Hyun KWON ,  Su-Hyeon KIM ,  Jun Mo PARK ,  Kyu Bong CHOI

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/775 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392

Abstract: A semiconductor device includes a first active pattern including a first lower pattern and first sheet patterns; a second active pattern including a second lower pattern and second sheet patterns, a height of the second lower pattern being smaller than a height of the first lower pattern; a first gate structure on the first lower pattern; a second gate structure on the second lower pattern; a first source/drain pattern on the first lower pattern and connected to the first sheet patterns; and a second source/drain pattern on the second lower pattern and connected to the second sheet patterns, wherein a width of an upper surface of the first lower pattern is different from a width of an upper surface of the second lower pattern, and wherein a number of first sheet patterns is different from a number of second sheet patterns.

公开(公告)号：US20230031546A1

公开(公告)日：2023-02-02

申请号：US17691438

申请日：2022-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Mo PARK ,  Yeon Ho PARK ,  Wang Seop LIM

IPC: H01L29/423 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238

Abstract: There is provided a semiconductor device capable of improving the performance and reliability of a device. The semiconductor device including an active pattern extending in a first direction, a gate structure on the active pattern, the gate structure extending in a second direction different from the first direction and including a gate insulating layer and a gate filling layer, a gate spacer extending in the second direction, on a sidewall of the gate structure, a gate shield insulating pattern on a sidewall of the gate spacer, covering an upper surface of the gate insulating layer, and including an insulating material, and a gate capping pattern covering an upper surface of the gate filling layer, on the gate structure may be provided.

公开(公告)号：US20170168829A1

公开(公告)日：2017-06-15

申请号：US15371408

申请日：2016-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Mo PARK ,  Ju Hwan KIM ,  Min Seong KIM ,  Yun Ji KIM ,  Taek Hyun KIM ,  Kyung Il SUN ,  Myeong Bo SHIM ,  Dong Hoon YU ,  Hye Yeon CHUNG ,  Sung Hyun HONG

IPC: G06F9/38 ,  G06F12/0875 ,  G06F9/30

CPC classification number: G06F9/384 ,  G06F9/30072 ,  G06F9/30101 ,  G06F9/3832 ,  G06F9/3836 ,  G06F9/3855 ,  G06F12/0875 ,  G06F2212/452

Abstract: A processor includes a first architectural register configured to store first data based on a result of executing an instruction in a first loop, the first architectural register being mapped to one of a plurality of physical registers; and a control unit configured to determine, before execution of the instruction in an n-th loop (n being a natural number greater than 1), at least one of whether the first data stored in the first architectural register is changed and whether a physical register, among the plurality of physical registers, to which the first architectural register is mapped is changed, and, based on a result of determination, execute the instruction in the n-th loop.