公开(公告)号：US20240136430A1

公开(公告)日：2024-04-25

申请号：US18201878

申请日：2023-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongmin SHIN ,  Wook Hyun KWON ,  Su-Hyeon KIM ,  Jun Mo PARK ,  Kyu Bong CHOI

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/775 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392

Abstract: A semiconductor device includes a first active pattern including a first lower pattern and first sheet patterns; a second active pattern including a second lower pattern and second sheet patterns, a height of the second lower pattern being smaller than a height of the first lower pattern; a first gate structure on the first lower pattern; a second gate structure on the second lower pattern; a first source/drain pattern on the first lower pattern and connected to the first sheet patterns; and a second source/drain pattern on the second lower pattern and connected to the second sheet patterns, wherein a width of an upper surface of the first lower pattern is different from a width of an upper surface of the second lower pattern, and wherein a number of first sheet patterns is different from a number of second sheet patterns.

公开(公告)号：US20230086174A1

公开(公告)日：2023-03-23

申请号：US17852658

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Mo PARK ,  Yeon Ho PARK ,  Eun Sil PARK ,  Jin Seok LEE ,  Wang Seop LIM ,  Kyu Bong CHOI

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/775 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/66

Abstract: A semiconductor device includes first and second sheet patterns spaced apart from each other on a first region of the substrate, a first gate electrode extending between the first and second sheet patterns, third and fourth sheet patterns spaced apart from each other on a second region of the substrate, and a second gate electrode extending between the third and fourth sheet patterns. The first gate electrode includes a first work function controlling film, which is between the first and second sheet patterns, and a first filling conductive film on the first work function controlling film. The second gate electrode includes a second work function controlling film, which is between the third and fourth sheet patterns, and a second filling conductive film on the second work function controlling film. A distance between the third and fourth sheet patterns is greater than a distance between the first and second sheet patterns.

公开(公告)号：US20240234558A9

公开(公告)日：2024-07-11

申请号：US18201878

申请日：2023-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongmin SHIN ,  Wook Hyun KWON ,  Su-Hyeon KIM ,  Jun Mo PARK ,  Kyu Bong CHOI

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/775 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392

Abstract: A semiconductor device includes a first active pattern including a first lower pattern and first sheet patterns; a second active pattern including a second lower pattern and second sheet patterns, a height of the second lower pattern being smaller than a height of the first lower pattern; a first gate structure on the first lower pattern; a second gate structure on the second lower pattern; a first source/drain pattern on the first lower pattern and connected to the first sheet patterns; and a second source/drain pattern on the second lower pattern and connected to the second sheet patterns, wherein a width of an upper surface of the first lower pattern is different from a width of an upper surface of the second lower pattern, and wherein a number of first sheet patterns is different from a number of second sheet patterns.

公开(公告)号：US20230040132A1

公开(公告)日：2023-02-09

申请号：US17741711

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Mo PARK ,  Kyu Bong CHOI ,  Yeon Ho PARK ,  Eun Sil PARK ,  Jin Seok LEE ,  Wang Seop LIM ,  Kyung In CHOI

IPC: H01L21/02 ,  H01L21/8234 ,  H01L21/768

Abstract: A method of manufacturing a semiconductor device includes: forming first to third preliminary active patterns on a substrate to have different intervals therebetween, forming first and second field insulating layers between the first and second preliminary active patterns and between the second and third preliminary active patterns, respectively, and forming first to third gate electrodes respectively on first to third active patterns formed based on the first to third preliminary active patterns, separated by first and second gate isolation structures.