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公开(公告)号:US20170266957A1
公开(公告)日:2017-09-21
申请号:US15254019
申请日:2016-09-01
Applicant: SAMSUNG DISPLAY CO., LTD. , SAMSUNG ELECTRONICS CO., LTD.
Inventor: Dongjun LEE , Minsoo KIM , Jongwon KIM , Seungdon LEE , Hyunjin LEE
IPC: B41J2/045 , H01L51/52 , G02F1/1341 , G02F1/133 , G02F1/1337 , H01L51/56 , H01L27/32
CPC classification number: B41J2/04541 , B41J2/04586 , G02F1/1303 , G02F1/13306 , G02F1/1337 , G02F1/1341 , H01L27/3244 , H01L51/0005 , H01L51/5253 , H01L51/56 , H01L2227/323 , H01L2251/558
Abstract: An inkjet printing method includes: setting a first region to be printed at a constant print density within a target region to be printed; setting a second region within the target region and closer than the first region to an edge of the target region, wherein the second region is to be printed at a print density that varies according to a position; generating control data for a plurality of nozzles provided on an inkjet head in order to print the first region and the second region; and driving the inkjet head according to the control data.
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公开(公告)号:US20230229841A1
公开(公告)日:2023-07-20
申请号:US18151051
申请日:2023-01-06
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hyunjae JANG , Jongwon KIM , In HUH , Satbyul KIM , Younggu KIM , Yunjun NAM , Changwook JEONG , Moonhyun CHA
IPC: G06F30/392 , G06F30/398
CPC classification number: G06F30/392 , G06F30/398 , G06F2119/02
Abstract: A method for simulating a layout of an integrated circuit manufactured by a semiconductor process includes extracting a plurality of pattern layouts from layout data that defines the layout, generating training data by amplifying the plurality of pattern layouts and at least one parameter provided from the semiconductor process, generating sample data by sampling the training data, generating feature data including a three-dimensional array from the sample data, providing the sample data and the feature data to a simulator and a machine learning model, respectively, and training the machine learning model based on an output of the machine learning model and an output of the simulator.
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公开(公告)号:US20230224395A1
公开(公告)日:2023-07-13
申请号:US18167497
申请日:2023-02-10
Applicant: Samsung Electronics Co., Ltd.
Inventor: Cheolhong SON , Gyusub KIM , Jongwon KIM , Kyungmoon SEOL , Jungkyu LEE , Bumjin CHO
CPC classification number: H04M1/0277 , H04M1/0216 , H04M1/0268 , H01Q1/243 , H04M2201/08
Abstract: An electronic device is provided. The electronic device includes a housing including a first housing and a second housing connected to the first housing by a hinge structure to be rotatable around a first axis, a magnet structure disposed inside the housing, the magnet structure including a magnet and a conductive coating member for enclosing a surface of the magnet, and a wireless communication circuit electrically connected to the conductive coating member, wherein the magnet is disposed to maintain a folding state in which the first housing and the second housing are folded, and the wireless communication circuit is configured to feed a portion of the conductive coating member of the magnet structure to transmit and/or receive a signal in a designated first frequency band by using at least one of the conductive coating member as a first antenna radiator.
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公开(公告)号:US20220415909A1
公开(公告)日:2022-12-29
申请号:US17903315
申请日:2022-09-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Haemin LEE , Jongwon KIM , Shinhwan KANG , Kohji KANAMORI , Jeehoon HAN
IPC: H01L27/1157 , H01L27/11578 , H01L27/11521 , H01L27/11556
Abstract: A semiconductor device includes a first stack group having first interlayer insulating layers and first gate layers, alternately and repeatedly stacked on a substrate and a second stack group comprising second interlayer insulating layers and second gate layers, alternately and repeatedly stacked on the first stack group. Separation structures pass through the first and second stack groups and include a first separation region and a second separation region. A vertical structure passes through the first and second stack groups and includes a first vertical region and a second vertical region. A conductive line is electrically connected to the vertical structure on the second stack group. A distance between an upper end of the first vertical region and an upper surface of the substrate is greater than a distance between an upper end of the first separation region and an upper surface of the substrate.
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公开(公告)号:US20250087886A1
公开(公告)日:2025-03-13
申请号:US18943407
申请日:2024-11-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jaehyung KIM , Hongpyo BAE , Seunghwan KIM , Jongwon KIM , Taegyu KIM , Jesun MOON , Himchan YUN , Jaebong CHUN , Hochul HWANG
Abstract: An electronic device includes a display, a rear cover, a side member surrounding the space between the display and the rear cover, the side member having a groove formed therein, a side key disposed the groove and including a conductive portion, a wireless communication circuit, at least one processor, and a first conductive connection member electrically connecting the at least one processor to the side key. The wireless communication circuit is configured to feed power to a first portion of the side member surrounding an edge of the groove through the first conductive connection member electrically connecting the at least one processor to the side key, and transmit and/or receive radio frequency (RF) signals in a specified frequency band, based on an electrical path formed in the first portion of the side member and the conductive portion of the side key.
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公开(公告)号:US20210035987A1
公开(公告)日:2021-02-04
申请号:US16844234
申请日:2020-04-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Haemin LEE , Jongwon KIM , Shinhwan KANG , Kohji KANAMORI , Jeehoon HAN
IPC: H01L27/1157 , H01L27/11578 , H01L27/11521 , H01L27/11556
Abstract: A semiconductor device includes a first stack group having first interlayer insulating layers and first gate layers, alternately and repeatedly stacked on a substrate and a second stack group comprising second interlayer insulating layers and second gate layers, alternately and repeatedly stacked on the first stack group. Separation structures pass through the first and second stack groups and include a first separation region and a second separation region. A vertical structure passes through the first and second stack groups and includes a first vertical region and a second vertical region. A conductive line is electrically connected to the vertical structure on the second stack group. A distance between an upper end of the first vertical region and an upper surface of the substrate is greater than a distance between an upper end of the first separation region and an upper surface of the substrate.
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公开(公告)号:US20190035807A1
公开(公告)日:2019-01-31
申请号:US15991476
申请日:2018-05-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jongwon KIM , Young-Jin JUNG
IPC: H01L27/11582 , H01L27/11556 , H01L27/11526 , H01L27/11573 , H01L29/792
Abstract: A three-dimensional semiconductor memory device and a method of manufacturing the same. The device may include a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, a plurality of first vertical structures penetrating the electrode structures on the cell array region, and a plurality of second vertical structures penetrating the electrode structures on the connection region. Each of the first and second vertical structures may include a lower semiconductor pattern connected to the substrate and an upper semiconductor pattern connected to the lower semiconductor pattern.
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公开(公告)号:US20240033578A1
公开(公告)日:2024-02-01
申请号:US18482146
申请日:2023-10-06
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hongyoon KIM , Jaehun HYEON , Dongwoo KIM , Kiljong KIM , Jongwon KIM , Seungyeon EOM , Kiwan LEE , Hyunkook CHO , Sukwon CHOI , Kwanghyung LEE , Myeonghee JEON , Yuchang JEONG , Jiwon HA
IPC: A63B24/00
CPC classification number: A63B24/0075
Abstract: An exercise program determining method and/or system may include obtaining basic exercise information of a user, determining at least one candidate exercise mode from among a plurality of exercise modes based on the basic exercise information, generating a plurality of exercise programs to include at least some of the at least one candidate exercise mode based on a target exercise result for the user, determining a target exercise amount for the user based on the basic exercise information, and determining a target exercise program from among the plurality of exercise programs based on the target exercise amount.
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公开(公告)号:US20230364465A1
公开(公告)日:2023-11-16
申请号:US18328252
申请日:2023-06-02
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hongyoon KIM , Kiljong KIM , Jongwon KIM , Seokwoo SONG , Hyunkook CHO
CPC classification number: A63B24/0003 , G06T7/68 , G06T7/70 , G06V10/44 , G06V40/23 , G06V2201/07 , G06T2207/20084 , G06T2207/30196
Abstract: An electronic apparatus is disclosed. The electronic apparatus includes: a memory including at least one instruction, a processor coupled with the memory and configured to control the electronic apparatus, and the processor is configured, by executing the at least one instruction, to: obtain a moving image, identify a person and pose data of the person from a plurality of frames in the moving image, obtain exercise pattern information corresponding to the plurality of frames using pose data of the identified person, recognize an exercise motion of the identified person by inputting at least one frame of the moving image into at least one neural network model, and obtain exercise feature information corresponding to the recognized exercise motion, identify, based on the exercise feature information and the exercise pattern information, a first frame interval and a second frame interval different from the first frame interval from among the plurality of frames in the moving image, and provide information on an exercise motion corresponding to the second frame interval by comparing the first frame interval with the second frame interval.
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公开(公告)号:US20190139984A1
公开(公告)日:2019-05-09
申请号:US16220836
申请日:2018-12-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jongwon KIM , Keejeong Rho , Jin-Yeon Won , Tae-Wan Lim , Woohyun Park
IPC: H01L27/11582 , H01L27/11565
CPC classification number: H01L27/11582 , H01L27/11565
Abstract: Semiconductor memory devices and methods for manufacturing the same are provided. The device may include vertical channel structures that are two-dimensionally arranged on a substrate and vertically extend from the substrate. The device may also include bit lines on the vertical channel structures, and each of the bit lines may be commonly connected to the vertical channel structures arranged in a first direction. The device may further include common source lines that extend between the vertical channel structures in a second direction intersecting the first direction and a source strapping line that is disposed at the same vertical level as the bit lines and electrically connects the common source lines to each other.
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