公开(公告)号：US20220293633A1

公开(公告)日：2022-09-15

申请号：US17825619

申请日：2022-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek JUNG ,  JoongShik SHIN ,  JiHye YUN

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L21/768 ,  H01L27/11573 ,  H01L23/528 ,  H01L23/532 ,  H01L21/285 ,  H01L27/1157 ,  H01L21/28

Abstract: A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.

公开(公告)号：US20240090224A1

公开(公告)日：2024-03-14

申请号：US18515536

申请日：2023-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek JUNG ,  JoongShik Shin ,  JiHye YUN

IPC: H10B43/27 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L21/28525 ,  H01L21/76868 ,  H01L23/528 ,  H01L23/53271 ,  H01L29/40114 ,  H01L29/40117 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40 ,  H01L23/5226 ,  H01L23/5283

Abstract: A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.

公开(公告)号：US20190333931A1

公开(公告)日：2019-10-31

申请号：US16192859

申请日：2018-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek JUNG ,  JoongShik SHIN ,  JiHye YUN

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L21/28 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/528 ,  H01L23/532 ,  H01L21/285 ,  H01L21/768

Abstract: A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.