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    CAPACITOR STRUCTURE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
    3.
    发明申请
    CAPACITOR STRUCTURE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20250016978A1

    公开(公告)日：2025-01-09

    申请号：US18613471

    申请日：2024-03-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung Min PARK ,  Ji-Sung KIM ,  Hae Ryong KIM ,  Bo-Eun PARK ,  Han Jin LIM ,  Hyung Suk JUNG

    IPC: H10B12/00

    Abstract: A capacitor structure is provided. The capacitor structure comprises an upper electrode, a lower electrode including a lower electrode film and a lower interface electrode film, a capacitor dielectric film between the lower electrode and the upper electrode, and an interface blocking film between the lower electrode and the capacitor dielectric film, the interface blocking film being in contact with the capacitor dielectric film and the lower interface electrode film, wherein the interface blocking film includes a first metal oxide containing a first metal element, the lower interface electrode film includes a second conductive metal oxide containing a second metal element different from the first metal element, the capacitor dielectric film does not include the first metal oxide, and a thickness of the lower interface electrode film is greater than that of the interface blocking film.

    SEMICONDUCTOR MEMORY DEVICE
    4.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240315045A1

    公开(公告)日：2024-09-19

    申请号：US18495038

    申请日：2023-10-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungmin PARK ,  Ji-Sung KIM ,  Hanjin LIM ,  Hyungsuk JUNG

    IPC: H10B53/30

    CPC classification number: H10B53/30

    Abstract: A semiconductor device may include a substrate including a first impurity region and a second impurity region; a first word line in a region of the substrate with the first impurity region on one side of the first word line and the second impurity region on an other side of the first word line; a bit line connected to the first impurity region; a first conductive pattern connected to the second impurity region; a first partial electrode and a second partial electrode on the first conductive pattern; a first dielectric layer in contact with an upper surface of the first partial electrode and an upper surface of the second partial electrode; and a common electrode on the first dielectric layer. An area of the upper surface of the first partial electrode may be different from an area of the upper surface of the second partial electrode.

    INTEGRATED CIRCUIT AND APPARATUSES INCLUDING THE SAME
    5.
    发明申请
    INTEGRATED CIRCUIT AND APPARATUSES INCLUDING THE SAME 有权
    集成电路及其设备

    公开(公告)号：US20130322177A1

    公开(公告)日：2013-12-05

    申请号：US13835780

    申请日：2013-03-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Eui-Seung KIM ,  Ji-Sung KIM

    IPC: G11C7/12 ,  G11C16/24

    CPC classification number: G11C7/12 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/28

    Abstract: An integrated includes a memory cell, a bit line connected to the memory cell, a boosting circuit to boost the bit line up to a boosting voltage during a pre-charge operation pre-charging the bit line, and a regulation circuit connected between the bit line and an output terminal and determines a logic level of the output terminal according to the voltage of the bit line.

    Abstract translation: 集成包括存储器单元，连接到存储单元的位线，在预充电位线的预充电操作期间将位线升高到升压电压的升压电路，以及连接在位之间的调节电路 线路和输出端子，并根据位线的电压确定输出端子的逻辑电平。

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