公开(公告)号：US09087842B2

公开(公告)日：2015-07-21

申请号：US14304750

申请日：2014-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Shigenobu Maeda ,  Ji-Hoon Yoon ,  Sung-Man Lim

IPC: H01L27/10 ,  H01L29/00 ,  H01L23/525 ,  H01L23/522

CPC classification number: H01L23/5256 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate having a fuse area and a device area; a fuse structure in an insulating layer of the fuse area, and a wire structure in the insulating layer of the device area. The fuse structure includes a fuse via, a fuse line electrically connected to a top end of the fuse via pattern and extending in a direction. The wire structure includes a wire via, a wire line electrically connected to a top end of the wire via and extending in the first direction. A width in the first direction of the fuse via is smaller than a width in the first direction of the wire via.

Abstract translation: 半导体器件包括具有熔丝区域和器件区域的衬底; 保险丝区域的绝缘层中的熔丝结构，以及设备区域的绝缘层中的线结构。 熔丝结构包括熔丝通孔，熔丝线与熔丝通孔图案的顶端电连接并沿一个方向延伸。 导线结构包括导线通孔，电线连接到导线通孔的顶端并沿第一方向延伸的导线。 保险丝通孔的第一方向上的宽度小于电线通路的第一方向上的宽度。

公开(公告)号：US09627390B2

公开(公告)日：2017-04-18

申请号：US14683151

申请日：2015-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Shigenobu Maeda ,  Ji-Hoon Yoon

IPC: H01L27/112 ,  G11C17/16 ,  H01L23/525

CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L23/5252 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A semiconductor device is provided. The semiconductor device includes: a plurality of fin-type active patterns which extend along a first direction, and are arranged with respect to each other along a second direction different from the first direction; a contact which is electrically connected to the plurality of fin-type active patterns; a first gate electrode which extends along the second direction and is formed on at least two of the plurality of fin-type active patterns; and a second gate electrode which extends along the second direction and is formed on at least one of the plurality of fin-type active patterns. The first gate electrode is disposed between the contact and the second gate electrode, and the number of fin-type active patterns intersected by the first gate electrode is greater than the number of fin-type active patterns intersected by the second gate electrode.

公开(公告)号：US09336894B2

公开(公告)日：2016-05-10

申请号：US14753620

申请日：2015-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Shigenobu Maeda ,  Ji-Hoon Yoon

IPC: G11C17/00 ,  G11C17/08 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C11/5685 ,  G11C11/5692 ,  G11C13/0007 ,  G11C13/0069 ,  G11C17/165 ,  G11C17/18 ,  G11C2213/53

Abstract: A memory device may include nonvolatile memory cells. A first memory cell of the nonvolatile memory cells may have a first resistance value in a first state and a second memory cell of the nonvolatile memory cells may have a second resistance value less than the first resistance value in a second state. A third memory cell of the nonvolatile memory cells may have a third resistance value less than the first resistance value and greater than the second resistance value in a third state, and a fourth memory cell of the nonvolatile memory cells may have a fourth resistance value less than the third resistance value and greater than the second resistance value in a fourth state.

Abstract translation: 存储器件可以包括非易失性存储器单元。 非易失性存储器单元的第一存储单元可以具有第一状态的第一电阻值，并且非易失性存储单元的第二存储单元可具有小于第二状态的第一电阻值的第二电阻值。 非易失性存储单元的第三存储单元可具有小于第一电阻值的第三电阻值并且大于第三状态中的第二电阻值，并且非易失性存储单元的第四存储单元可具有较小的第四电阻值 大于第四电阻值且大于第四电阻值。