公开(公告)号：US09882074B2

公开(公告)日：2018-01-30

申请号：US14940696

申请日：2015-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyun Yang ,  Hyena Kwak ,  Hyoungsub Kim ,  Hoojeong Lee ,  Seongjun Park ,  Seongjun Jeong

IPC: H01L31/0336 ,  H01L31/112 ,  H01L31/032

CPC classification number: H01L31/0336 ,  H01L31/032 ,  H01L31/1129

Abstract: An optoelectronic device is disclosed. The disclosed optoelectronic device includes an oxide semiconductor layer and a semiconducting two-dimensional (2D) material layer forming a stack structure with the oxide semiconductor layer.

公开(公告)号：US10797074B2

公开(公告)日：2020-10-06

申请号：US16379063

申请日：2019-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyun Yang ,  Bio Kim ,  Yujin Kim ,  Kyong-Won An ,  Sookyeom Yong ,  Junggeun Jee ,  Youngjun Cheon

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first stack structure on a substrate including a cell array region and a connection region, a second stack structure on the first stack structure, a first vertical channel hole penetrating the first stack structure and partially exposing the substrate and a bottom surface of the second stack structure, on the cell array region, a second vertical channel hole penetrating the second stack structure and exposing the first vertical channel hole, on the cell array region, a bottom diameter of the second vertical channel hole being smaller than an top diameter of the first vertical channel hole, and a buffer pattern placed in the first vertical channel hole and adjacent to the bottom surface of the second stack structure.

公开(公告)号：US11569261B2

公开(公告)日：2023-01-31

申请号：US17005495

申请日：2020-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyun Yang ,  Bio Kim ,  Yujin Kim ,  Kyong-Won An ,  Sookyeom Yong ,  Junggeun Jee ,  Youngjun Cheon

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first stack structure on a substrate including a cell array region and a connection region, a second stack structure on the first stack structure, a first vertical channel hole penetrating the first stack structure and partially exposing the substrate and a bottom surface of the second stack structure, on the cell array region, a second vertical channel hole penetrating the second stack structure and exposing the first vertical channel hole, on the cell array region, a bottom diameter of the second vertical channel hole being smaller than an top diameter of the first vertical channel hole, and a buffer pattern placed in the first vertical channel hole and adjacent to the bottom surface of the second stack structure.