公开(公告)号：US20210005509A1

公开(公告)日：2021-01-07

申请号：US17016537

申请日：2020-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JISEOK HONG ,  CHAN-SIC YOON ,  ILYOUNG MOON ,  JEMIN PARK ,  KISEOK LEE ,  JUNG-HOON HAN

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A method of fabricating a semiconductor device includes providing a substrate, and forming an interlayered insulating layer on the substrate. The method includes forming a preliminary via hole in the interlayered insulating layer. The method includes forming a passivation spacer on an inner side surface of the preliminary via hole. The method includes forming a via hole using the passivation spacer as an etch mask. The method includes forming a conductive via in the via hole. The passivation spacer includes an insulating material different from an insulating material included in the interlayered insulating layer.

公开(公告)号：US20220020758A1

公开(公告)日：2022-01-20

申请号：US17192086

申请日：2021-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEORYONG PARK ,  SEUNGUK HAN ,  Jiyoung AHN ,  Kiseok LEE ,  YOONYOUNG CHOI ,  JISEOK HONG

IPC: H01L27/11551 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11578 ,  G11C7/18 ,  G11C8/14

Abstract: A semiconductor memory device includes a substrate with a cell array region, a first interface region, and a second interface region, the cell array region being provided with active regions, bit lines on the cell array region and the second interface region, dielectric patterns on top surfaces of the bit lines and extending along the top surfaces of the bit lines and further extending onto the first interface region, a device isolation pattern on the substrate, and including a first portion on the cell array region and a second portion on the first interface region, the first portion defining the active regions, the second portion being provided with first recesses, and each first recess being disposed between two adjacent dielectric patterns, and first sacrificial semiconductor patterns disposed on the first interface region and in the first recesses. The first sacrificial semiconductor patterns include polycrystalline silicon.

公开(公告)号：US20210143116A1

公开(公告)日：2021-05-13

申请号：US17007223

申请日：2020-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： JISEOK HONG ,  HYUEKJAE LEE ,  JONGPA HONG ,  JIHWAN HWANG ,  TAEHUN KIM

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/48

Abstract: A semiconductor package includes a first semiconductor chip having a through-electrode and an upper connection pad on an upper surface of the first semiconductor chip that is connected to the through-electrode; a second semiconductor chip stacked on the first semiconductor chip, and having a lower connection pad on a lower surface of the second semiconductor chip; a non-conductive film between the first semiconductor chip and the second semiconductor chip, with the non-conductive film including voids having an average diameter of 1 μm to 100 μm, the voids having a volume fraction of 0.1 to 5 vol %; and a connection conductor that penetrates the non-conductive film and connects the upper connection pad and the lower connection pad.

公开(公告)号：US20220068863A1

公开(公告)日：2022-03-03

申请号：US17500079

申请日：2021-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： JISEOK HONG ,  HYUEKJAE LEE ,  JONGPA HONG ,  JIHWAN HWANG ,  TAEHUN KIM

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip having a through-electrode and an upper connection pad on an upper surface of the first semiconductor chip that is connected to the through-electrode; a second semiconductor chip stacked on the first semiconductor chip, and having a lower connection pad on a lower surface of the second semiconductor chip; a non- conductive film between the first semiconductor chip and the second semiconductor chip, with the non-conductive film including voids having an average diameter of 1μm to 100 um, the voids having a volume fraction of 0.1 to 5 vol %; and a connection conductor that penetrates the non- conductive film and connects the upper connection pad and the lower connection pad.

公开(公告)号：US20190122919A1

公开(公告)日：2019-04-25

申请号：US15984524

申请日：2018-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JISEOK HONG ,  CHAN-SIC YOON ,  ILYOUNG MOON ,  JEMIN PARK ,  KISEOK LEE ,  JUNG-HOON HAN

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method of fabricating a semiconductor device includes providing a substrate, and forming an interlayered insulating layer on the substrate. The method includes forming a preliminary via hole in the interlayered insulating layer. The method includes forming a passivation spacer on an inner side surface of the preliminary via hole. The method includes forming a via hole using the passivation spacer as an etch mask. The method includes forming a conductive via in the via hole. The passivation spacer includes an insulating material different from an insulating material included in the interlayered insulating layer.