公开(公告)号：US20150162201A1

公开(公告)日：2015-06-11

申请号：US14477273

申请日：2014-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-Hee Lee ,  Min-Woo Song ,  Seok-Jun Won ,  Hyung-Suk Jung

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L21/28247 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/28518 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure including a dummy gate electrode and a gate mask sequentially stacked on a substrate is formed. A spacer is formed on a sidewall of the dummy gate structure. The gate mask is formed to expose the dummy gate electrode and to form a recess on the spacer. A capping layer pattern is formed to fill the recess in the spacer. The exposed dummy gate electrode is replaced with a gate electrode.

Abstract translation: 在制造半导体器件的方法中，形成包括依次层叠在基板上的伪栅极电极和栅极掩模的虚拟栅极结构。 在虚拟栅极结构的侧壁上形成间隔物。 形成栅极掩模以暴露伪栅电极并在间隔物上形成凹陷。 形成覆盖层图案以填充间隔件中的凹部。 暴露的虚拟栅电极被栅电极代替。