公开(公告)号：US10396761B2

公开(公告)日：2019-08-27

申请号：US15669072

申请日：2017-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Chul Hwang ,  Min-Su Kim ,  Dae-Seong Lee

IPC: H03K3/012 ,  H03K3/356 ,  H03K3/3562

Abstract: A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.

公开(公告)号：US10651828B2

公开(公告)日：2020-05-12

申请号：US15623412

申请日：2017-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Chul Hwang ,  Ah-Reum Kim ,  Min-Su Kim

IPC: H03K3/012 ,  H03K3/3562 ,  H03K3/356 ,  H03K19/21

Abstract: A flip-flop generates a first feedback signal using a signal generated inside the flip-flop. The flip-flop includes a first stage circuit, a second stage circuit and a third stage circuit. The first stage circuit receives a first data signal and a clock signal and generates a first internal signal through a first node. The second stage circuit receives the first internal signal, the clock signal, and the first feedback signal and generates a second internal signal through a second node. The third stage circuit generates a second data signal by latching the second internal signal when the clock signal is at a first level, using the second internal signal and the clock signal. The second stage circuit cuts off at least one first current path between the second node and a power supply, based on the first feedback signal, when the clock signal is at a second level.

公开(公告)号：US10184984B2

公开(公告)日：2019-01-22

申请号：US15140720

申请日：2016-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Chul Hwang ,  Dae-Seong Lee ,  Min-Su Kim

IPC: G01R31/28 ,  G01R31/3185

Abstract: An integrated circuit and an electronic apparatus including the same. The electronic apparatus includes a scan input processing circuit, a selection circuit and a scanning circuit. The scan input processing unit is configured to output one of a scan input and a first logical value in response to a scan enable signal. The selection unit is configured to select one of an output of the scan input processing unit or a data input in response to the scan enable signal. The scan element comprises a flip-flop configured to store an output of the selection unit.

公开(公告)号：US10911032B2

公开(公告)日：2021-02-02

申请号：US16524609

申请日：2019-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Chul Hwang ,  Min-Su Kim ,  Dae-Seong Lee

IPC: H03K3/012 ,  H03K3/3562 ,  H03K3/356

Abstract: A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.

公开(公告)号：US10033386B2

公开(公告)日：2018-07-24

申请号：US15661153

申请日：2017-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Chul Hwang ,  Min-Su Kim

IPC: H03K19/018 ,  H03K3/037 ,  H03K19/0185 ,  H03K19/20 ,  H03K3/012 ,  H03K3/356

Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit is configured to generate a voltage level at a first node based on a voltage level of input data, an inverted value of the voltage level at the first node, a voltage level of a clock signal, and a voltage level at a second node; and the second circuit is configured to generate the voltage level at the second node based on the voltage level of input data, an inverted value of the voltage level at the second node, the voltage level of the clock signal, and the inverted value of the voltage level at the first node. When the clock signal is at a first level, the first and second nodes have different logical levels. When the clock signal is at a second level, the first and second nodes have the same logical level.

公开(公告)号：US10938383B2

公开(公告)日：2021-03-02

申请号：US15906693

申请日：2018-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Chul Hwang ,  Jong-Kyu Ryu ,  Min-Su Kim

IPC: H03K5/135 ,  H03K3/356 ,  H03K3/037 ,  H03K3/012 ,  H03K5/00 ,  H03K19/20 ,  H03K19/21

Abstract: A sequential circuit includes a first gate circuit, a second gate circuit and an output circuit. The first circuit generates a first signal based on an input signal, an input clock signal and a second signal. The second circuit generates an internal clock signal by performing a NOR operation on the first signal and an inversion clock signal which is inverted from the input clock signal, and generates the second signal based on the internal clock signal and the input signal. The output circuit generates an output signal based on the second signal. Operation speed of the sequential circuit and the integrated circuit including the same may be increased by increasing the negative setup time reflecting a transition of the input signal after a transition of the input clock signal, through mutual controls between the first circuit and the second circuit.

公开(公告)号：US09722611B2

公开(公告)日：2017-08-01

申请号：US15248099

申请日：2016-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Chul Hwang ,  Min-Su Kim

IPC: H03K19/00 ,  H03K3/012 ,  H03K19/0185 ,  H03K19/20 ,  H03K3/037 ,  H03K3/356

CPC classification number: H03K19/018521 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356104 ,  H03K3/356121 ,  H03K3/356139 ,  H03K19/0013 ,  H03K19/0016 ,  H03K19/20

Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit is configured to generate a voltage level at a first node based on a voltage level of input data, an inverted value of the voltage level at the first node, a voltage level of a clock signal, and a voltage level at a second node; and the second circuit is configured to generate the voltage level at the second node based on the voltage level of input data, an inverted value of the voltage level at the second node, the voltage level of the clock signal, and the inverted value of the voltage level at the first node. When the clock signal is at a first level, the first and second nodes have different logical levels. When the clock signal is at a second level, the first and second nodes have the same logical level.