公开(公告)号：US11735498B2

公开(公告)日：2023-08-22

申请号：US17213767

申请日：2021-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangwuk Park ,  Youngmin Lee ,  Sungdong Cho ,  Eunji Kim ,  Hyoungyol Mun ,  Seokhwan Jeong

IPC: H01L23/48 ,  H01L21/762 ,  H01L25/065 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76232

Abstract: A semiconductor includes a substrate having a first surface and a second surface opposite to each other, the substrate having a via hole extending in a thickness direction from the first surface, a circuit pattern in the first surface of the substrate, a through electrode structure in the via hole, a device isolation structure in a first trench extending in one direction in the first surface of the substrate, the device isolation structure between the via hole and the circuit pattern, the device isolation structure including a first oxide layer pattern and a first nitride layer pattern sequentially stacked on an inner surface of the first trench, the first nitride layer pattern filling the first trench, and an insulation interlayer on the first surface of the substrate and covering the circuit pattern.

公开(公告)号：US11532581B2

公开(公告)日：2022-12-20

申请号：US17158450

申请日：2021-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Uidam Jung ,  Hyoungyol Mun ,  Sangjun Park ,  Kyuha Lee

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor device includes a first structure including a first bonding structure, and a second structure on the first structure and including a second bonding structure connected to the first bonding structure. The first bonding structure includes a first insulating layer, a first bonding insulating layer on the first insulating layer, first bonding pads penetrating at least a portion of the first insulating layer and the first bonding insulating layer, and first metal patterns in the first insulating layer and in contact with the first bonding insulating layer, and having an upper surface at a lower level than upper surfaces of the first bonding pads. The second bonding structure includes a second bonding insulating layer bonded to the first bonding insulating layer, a second insulating layer on the second bonding insulating layer, and second bonding pads penetrating the second bonding insulating layer and connected to the first bonding pads.

公开(公告)号：US20250098155A1

公开(公告)日：2025-03-20

申请号：US18742376

申请日：2024-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsung Kang ,  Hyoungyol Mun ,  Youngmin Lee

IPC: H10B12/00

Abstract: A semiconductor device includes lower electrodes on a substrate, a support pattern between the lower electrodes, an upper electrode on the lower electrodes and the support pattern, and a dielectric layer between the lower electrodes and the upper electrode, and between the support pattern and the upper electrode. The upper electrode includes a first portion on upper surfaces of the lower electrodes and a second portion on a sidewall of the support pattern. The first portion is thicker than the second portion.

公开(公告)号：US20220068859A1

公开(公告)日：2022-03-03

申请号：US17207242

申请日：2021-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungeun Choi ,  Eun-Ji Kim ,  Jong-Ho Moon ,  Hyoungyol Mun ,  Han-Sik Yoo ,  Kiseok Lee ,  Seungjae Jung ,  Taehyun An ,  Sangyeon Han ,  Yoosang Hwang

IPC: H01L23/00 ,  H01L27/108 ,  G11C11/408 ,  G11C11/4091 ,  H01L25/065 ,  H01L25/18

Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first substrate including a bit-line connection region and a word-line connection region, a cell array structure on the first substrate, a second substrate including a first core region and a second core region, which are respectively overlapped with the bit-line connection region and the word-line connection region, and a peripheral circuit structure on the second substrate.

公开(公告)号：US11791242B2

公开(公告)日：2023-10-17

申请号：US17371602

申请日：2021-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangwuk Park ,  Youngmin Lee ,  Hyoungyol Mun ,  Inyoung Lee ,  Seokhwan Jeong ,  Sungdong Cho

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/5283 ,  H01L23/5286 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06586

Abstract: A semiconductor device, includes: a substrate having a first surface on which a plurality of devices are disposed and a second surface, opposite to the first surface; an interlayer insulating film on the first surface of the substrate; an etching delay layer disposed in a region between the substrate and the interlayer insulating film; first and second landing pads on the interlayer insulating film; a first through electrode penetrating through the substrate and the interlayer insulating film; and a second through electrode penetrating the substrate, the etching delay layer, and the interlayer insulating film, the second through electrode having a width, greater than that of the first through electrode, wherein each of the first and second through electrodes includes first and second tapered end portions in the interlayer insulating film, each of first and second tapered end portions having a cross-sectional shape narrowing closer to the landing pads.

公开(公告)号：US11410951B2

公开(公告)日：2022-08-09

申请号：US17207242

申请日：2021-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungeun Choi ,  Eun-Ji Kim ,  Jong-Ho Moon ,  Hyoungyol Mun ,  Han-Sik Yoo ,  Kiseok Lee ,  Seungjae Jung ,  Taehyun An ,  Sangyeon Han ,  Yoosang Hwang

IPC: H01L27/108 ,  G11C11/408 ,  H01L25/065 ,  G11C11/4091 ,  H01L23/00 ,  H01L25/18

Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first substrate including a bit-line connection region and a word-line connection region, a cell array structure on the first substrate, a second substrate including a first core region and a second core region, which are respectively overlapped with the bit-line connection region and the word-line connection region, and a peripheral circuit structure on the second substrate.