公开(公告)号：US11735498B2

公开(公告)日：2023-08-22

申请号：US17213767

申请日：2021-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangwuk Park ,  Youngmin Lee ,  Sungdong Cho ,  Eunji Kim ,  Hyoungyol Mun ,  Seokhwan Jeong

IPC: H01L23/48 ,  H01L21/762 ,  H01L25/065 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76232

Abstract: A semiconductor includes a substrate having a first surface and a second surface opposite to each other, the substrate having a via hole extending in a thickness direction from the first surface, a circuit pattern in the first surface of the substrate, a through electrode structure in the via hole, a device isolation structure in a first trench extending in one direction in the first surface of the substrate, the device isolation structure between the via hole and the circuit pattern, the device isolation structure including a first oxide layer pattern and a first nitride layer pattern sequentially stacked on an inner surface of the first trench, the first nitride layer pattern filling the first trench, and an insulation interlayer on the first surface of the substrate and covering the circuit pattern.

公开(公告)号：US11791242B2

公开(公告)日：2023-10-17

申请号：US17371602

申请日：2021-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangwuk Park ,  Youngmin Lee ,  Hyoungyol Mun ,  Inyoung Lee ,  Seokhwan Jeong ,  Sungdong Cho

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/5283 ,  H01L23/5286 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06586

Abstract: A semiconductor device, includes: a substrate having a first surface on which a plurality of devices are disposed and a second surface, opposite to the first surface; an interlayer insulating film on the first surface of the substrate; an etching delay layer disposed in a region between the substrate and the interlayer insulating film; first and second landing pads on the interlayer insulating film; a first through electrode penetrating through the substrate and the interlayer insulating film; and a second through electrode penetrating the substrate, the etching delay layer, and the interlayer insulating film, the second through electrode having a width, greater than that of the first through electrode, wherein each of the first and second through electrodes includes first and second tapered end portions in the interlayer insulating film, each of first and second tapered end portions having a cross-sectional shape narrowing closer to the landing pads.