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公开(公告)号：US20210088245A1
公开(公告)日：2021-03-25
申请号：US17004445
申请日：2020-08-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyeonje CHO , Inhwan HWANG , Huijung KIM , Yunhu JI , Sehoon KIM
Abstract: An operation method for reducing energy consumption and an electronic apparatus thereof are provided. The operation method includes obtaining, by the electronic apparatus, weather forecast information, inputting, by the electronic apparatus, the weather forecast information to an artificial intelligence model for predicting an amount of power to be consumed by a first air conditioner, and displaying, by the electronic apparatus, the predicted power consumption amount of the first air conditioner output from the artificial intelligence model, wherein the artificial intelligence model is trained to obtain correlation information between a weather condition and a power consumption amount of an air conditioner, based on a weather history and operations of a plurality of air conditioners related to the weather history, and predict the amount of power to be consumed by the first air conditioner based on the correlation information and the weather forecast information.
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公开(公告)号：US20210358913A1
公开(公告)日：2021-11-18
申请号：US17092593
申请日：2020-11-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyuncheol KIM , Yongseok KIM , Huijung KIM , Satoru YAMADA , Sungwon YOO , Kyunghwan LEE , Jaeho HONG
IPC: H01L27/102 , H01L29/74
Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.
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公开(公告)号：US20240290868A1
公开(公告)日：2024-08-29
申请号：US18404607
申请日：2024-01-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Taejin PARK , Bongsoo KIM , Huijung KIM
CPC classification number: H01L29/6656 , H01L29/0649 , H10B12/315
Abstract: A semiconductor device includes a first structure including a first impurity region, a second impurity region, and an isolation region, a second structure on the first structure and including a contact opening penetrating through the second structure and exposing the first impurity region, a pattern structure including a contact portion connected to the first impurity region in the contact opening, and a line portion on the contact portion and the second structure, and a spacer structure between a side surface of the contact opening and the contact portion. The spacer structure includes a first spacer layer on the side surface of the contact opening, and a second spacer layer between the first spacer layer and the contact portion. A lower end of the second spacer layer is at a higher level than a lower surface of the contact portion.
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公开(公告)号：US20220344341A1
公开(公告)日：2022-10-27
申请号：US17558855
申请日：2021-12-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Huijung KIM , Myeongdong LEE , Inwoo KIM , Sunghee HAN
IPC: H01L27/108 , H01L21/768 , H01L23/528
Abstract: A semiconductor device that includes a substrate including an active region and a contact recess. A gate electrode is disposed in the substrate and extends in a first direction. A bit line structure intersects the gate electrode and extends in a second direction intersecting the first direction. The bit line structure includes a direct contact disposed in the contact recess. A buried contact is disposed on the substrate and is electrically connected to the active region. A spacer structure is disposed between the bit line structure and the buried contact. The spacer structure includes a buried spacer disposed on a lateral side surface of the direct contact, and an air gap disposed on the buried spacer. The air gap exposes a lateral side surface of the bit line structure.
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公开(公告)号：US20240315005A1
公开(公告)日：2024-09-19
申请号：US18388266
申请日：2023-11-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kiseok LEE , Sangjae PARK , Huijung KIM , Taejin PARK , Chansic YOON , Myeongdong LEE
IPC: H10B12/00
CPC classification number: H10B12/315 , H10B12/0335 , H10B12/482
Abstract: A semiconductor device includes an active pattern array including active patterns on a substrate; a first contact structure on a central portion of each active pattern; a bit line structure on the first contact structure; a second contact structure on an end of each active pattern; a third contact structure on the second contact structure; and a capacitor electrically connected to the third contact structure, wherein the active pattern array includes active pattern rows spaced apart from each other in a second direction parallel the substrate, the active pattern rows include active patterns spaced apart from each other in a first direction parallel to the substrate, the active patterns extend in a third direction having an acute angle with the first/second directions, the active patterns in the rows are aligned in the first direction, and the second contact structure has a rectangular shape in a plan view.
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Patent Agency Ranking
公开(公告)号：US20240130112A1
公开(公告)日：2024-04-18
申请号：US18464475
申请日：2023-09-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Taejin PARK , Bongsoo KIM , Huijung KIM
IPC: H10B12/00
CPC classification number: H10B12/34 , H10B12/053 , H10B12/485 , H10B12/488
Abstract: Provided is an integrated circuit device including a substrate that has an active region defined by a plurality of device separation regions, a word line on the substrate and arranged in a word line trench that extends in a first horizontal direction, a bit line on the word line and extending in a second horizontal direction orthogonal to the first horizontal direction, a pad on the active region and having a horizontal width that is larger than the active region, and a bit line contact electrically connecting the bit line to the active region, wherein a level of a lowermost surface of the additional pad is at a same vertical level as a level of a lowermost surface of the bit line contact.
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公开(公告)号：US20230087048A1
公开(公告)日：2023-03-23
申请号：US18071017
申请日：2022-11-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyeonje CHO , Inhwan HWANG , Huijung KIM , Yunhu JI , Sehoon KIM
Abstract: An operation method for reducing energy consumption and an electronic apparatus thereof are provided. The operation method includes obtaining, by the electronic apparatus, weather forecast information, inputting, by the electronic apparatus, the weather forecast information to an artificial intelligence model for predicting an amount of power to be consumed by a first air conditioner, and displaying, by the electronic apparatus, the predicted power consumption amount of the first air conditioner output from the artificial intelligence model, wherein the artificial intelligence model is trained to obtain correlation information between a weather condition and a power consumption amount of an air conditioner, based on a weather history and operations of a plurality of air conditioners related to the weather history, and predict the amount of power to be consumed by the first air conditioner based on the correlation information and the weather forecast information.
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公开(公告)号：US20250113590A1
公开(公告)日：2025-04-03
申请号：US18976522
申请日：2024-12-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyuncheol KIM , Yongseok KIM , Huijung KIM , Satoru YAMADA , Sungwon YOO , Kyunghwan LEE , Jaeho HONG
Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.
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公开(公告)号：US20240315010A1
公开(公告)日：2024-09-19
申请号：US18435198
申请日：2024-02-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Taejin PARK , Jongmin KIM , Huijung KIM , Kiseok LEE , Myeongdong LEE
IPC: H10B12/00
CPC classification number: H10B12/34 , H10B12/03 , H10B12/482 , H10B12/488
Abstract: Provided is a semiconductor device comprising: an active region defined by an element isolation film in a substrate; a word line extending in a first horizontal direction in the substrate; a bit line extending in a second horizontal direction crossing the first horizontal direction on the substrate; an additional pad disposed on the active region; and a buried contact on the additional pad wherein the buried contact is electrically connected to the active region by the additional pad, wherein the additional pad comprises a first surface that overlaps the word line in a vertical direction, and a second surface that is free of overlap with the word line in the vertical direction, and wherein, the first surface meets the second surface at a cusp.
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公开(公告)号：US20240032280A1
公开(公告)日：2024-01-25
申请号：US18224802
申请日：2023-07-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Taejin PARK , Kyujin KIM , Bongsoo KIM , Huijung KIM , Chulkwon PARK , Gyunghyun YOON , Heejae CHAE
IPC: H10B12/00
CPC classification number: H10B12/34 , H10B12/053
Abstract: An Integrated Circuit (IC) semiconductor device includes: field insulating layers buried in field trenches disposed apart from each other inside a substrate; active regions defined by the field insulating layers; and active fins disposed on the active regions and protruding from surfaces of the field insulating layers. The field insulating layers include a first subfield insulating layer and a second subfield insulating layer, and a surface of the first subfield insulating layer is disposed at a level lower than a level of a surface of the second subfield insulating layer.
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