SEMICONDUCTOR MEMORY DEVICE WITH STACKED CHIPS STRUCTURE

    公开(公告)号:US20250140751A1

    公开(公告)日:2025-05-01

    申请号:US18612283

    申请日:2024-03-21

    Abstract: A semiconductor memory device may include a first chip include a first array matrix and a second array matrix adjacent to each other and including memory cells, and a second chip below the first chip, and including sense amplifiers configured to drive the memory cells, where first cell bit lines are in the first array matrix, and second cell bit lines are in the second array matrix, where first bit lines and first complementary bit lines are below the first array matrix, and second bit lines and second complementary bit lines are below the second array matrix, and where the first bit lines and the second bit lines are connected to the first cell bit lines and the second cell bit lines, respectively, the first complementary bit lines and the second complementary bit lines are connected to the second cell bit lines and first cell bit lines, respectively.

    BIT LINE SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME

    公开(公告)号:US20240339153A1

    公开(公告)日:2024-10-10

    申请号:US18746974

    申请日:2024-06-18

    CPC classification number: G11C11/4091 G11C11/4094 G11C11/4097

    Abstract: A bit line sense amplifier includes a plurality of semiconductor devices including sensing transistors and selection transistors disposed side by side, and configured to sense a voltage change of a bit line and a complementary bit line, and wiring patterns connected to at least one of the plurality of semiconductor devices. The sensing transistors share a source electrode. The selection transistors may be controlled to be complementarily turned on and off. The wiring patterns include a first wiring pattern electrically connecting gate electrodes of the sensing transistors and drain electrodes of the selection transistors, and a second wiring pattern electrically connecting a gate electrode of a sensing transistor and a drain electrode of another sensing transistor.

    BIT LINE SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME

    公开(公告)号:US20230064611A1

    公开(公告)日:2023-03-02

    申请号:US17748357

    申请日:2022-05-19

    Abstract: A bit line sense amplifier includes a plurality of semiconductor devices including sensing transistors and selection transistors disposed side by side, and configured to sense a voltage change of a bit line and a complementary bit line, and wiring patterns connected to at least one of the plurality of semiconductor devices. The sensing transistors share a source electrode. The selection transistors may be controlled to be complementarily turned on and off. The wiring patterns include a first wiring pattern electrically connecting gate electrodes of the sensing transistors and drain electrodes of the selection transistors, and a second wiring pattern electrically connecting a gate electrode of a sensing transistor and a drain electrode of another sensing transistor.

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