公开(公告)号：US20250140751A1

公开(公告)日：2025-05-01

申请号：US18612283

申请日：2024-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoseok LEE ,  Kyu-Chang KANG ,  Kangsub JEONG ,  Dayoung KIM ,  Young Seok PARK

IPC: H01L25/065 ,  G11C11/4091 ,  H01L23/00 ,  H10B12/00 ,  H10B80/00

Abstract: A semiconductor memory device may include a first chip include a first array matrix and a second array matrix adjacent to each other and including memory cells, and a second chip below the first chip, and including sense amplifiers configured to drive the memory cells, where first cell bit lines are in the first array matrix, and second cell bit lines are in the second array matrix, where first bit lines and first complementary bit lines are below the first array matrix, and second bit lines and second complementary bit lines are below the second array matrix, and where the first bit lines and the second bit lines are connected to the first cell bit lines and the second cell bit lines, respectively, the first complementary bit lines and the second complementary bit lines are connected to the second cell bit lines and first cell bit lines, respectively.