公开(公告)号：US20220068968A1

公开(公告)日：2022-03-03

申请号：US17523014

申请日：2021-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hoon CHOI ,  Sung Gil KIM ,  Seulye KIM ,  Jung Ho KIM ,  Hong Suk KIM ,  Phil Ouk NAM ,  Jae Young AHN ,  Han Jin LIM

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11565

Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.

公开(公告)号：US20250016978A1

公开(公告)日：2025-01-09

申请号：US18613471

申请日：2024-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Min PARK ,  Ji-Sung KIM ,  Hae Ryong KIM ,  Bo-Eun PARK ,  Han Jin LIM ,  Hyung Suk JUNG

IPC: H10B12/00

Abstract: A capacitor structure is provided. The capacitor structure comprises an upper electrode, a lower electrode including a lower electrode film and a lower interface electrode film, a capacitor dielectric film between the lower electrode and the upper electrode, and an interface blocking film between the lower electrode and the capacitor dielectric film, the interface blocking film being in contact with the capacitor dielectric film and the lower interface electrode film, wherein the interface blocking film includes a first metal oxide containing a first metal element, the lower interface electrode film includes a second conductive metal oxide containing a second metal element different from the first metal element, the capacitor dielectric film does not include the first metal oxide, and a thickness of the lower interface electrode film is greater than that of the interface blocking film.

公开(公告)号：US20230352548A1

公开(公告)日：2023-11-02

申请号：US18219525

申请日：2023-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunae CHO ,  Dongjin LEE ,  Ji Eun LEE ,  Kyoung-Ho JUNG ,  Dong Su KO ,  Yongsu KIM ,  Jiho YOO ,  Sung HEO ,  Hyun PARK ,  Satoru YAMADA ,  Moonyoung JEONG ,  Sungjin KIM ,  Gyeongsu PARK ,  Han Jin LIM

IPC: H01L29/49 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/4236 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate including a trench. The semiconductor device further includes a gate electrode disposed in the trench, and a gate insulating film disposed between the substrate and the gate electrode. The gate electrode includes a gate conductor and a metal element, and an effective work function of the gate electrode is less than an effective work function of the gate conductor.

公开(公告)号：US20210020735A1

公开(公告)日：2021-01-21

申请号：US17030678

申请日：2020-09-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Yeol KANG ,  Kyu Ho CHO ,  Han Jin LIM ,  Cheol Seong HWANG

IPC: H01L49/02 ,  H01L27/108

Abstract: A semiconductor device including a switching element on a substrate, a pad isolation layer on the switching element, a conductive pad passing through the pad isolation layer and connected to the switching element, an insulating pattern on the pad isolation layer and having a height greater than a horizontal width, a lower electrode on side surfaces of the insulating pattern on side surfaces of the insulating pattern and in contact with the conductive pad, a capacitor dielectric layer on the lower electrode and having a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer an upper electrode on the capacitor dielectric layer may be provided.

公开(公告)号：US20230361161A1

公开(公告)日：2023-11-09

申请号：US18347850

申请日：2023-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han Jin LIM ,  Ki Nam KIM ,  Hyung Suk JUNG ,  Kyoo Ho JUNG ,  Ki Hyun HWANG

IPC: H01L21/28 ,  H01L21/02

CPC classification number: H01L28/56 ,  H01L21/02197 ,  H01L21/02192 ,  H01L21/02189 ,  H01L21/02181 ,  H01L21/28247 ,  H10B53/30 ,  H10B12/00

Abstract: There is provided a semiconductor device capable of improving the performance and/or reliability of the element, by increasing the capacitance of the capacitor, using a capacitor dielectric film including a ferroelectric material and a paraelectric material. The semiconductor device includes first and second electrodes disposed to be spaced apart from each other, and a capacitor dielectric film disposed between the first electrode and the second electrode and including a first dielectric film and a second dielectric film. The first dielectric film includes one of a first monometal oxide film and a first bimetal oxide film, the first dielectric film has an orthorhombic crystal system, the second dielectric film includes a paraelectric material, and a dielectric constant of the capacitor dielectric film is greater than a dielectric constant of the second dielectric film.

公开(公告)号：US20230225102A1

公开(公告)日：2023-07-13

申请号：US17964998

申请日：2022-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Intak JEON ,  Han Jin LIM

IPC: H01L27/108

CPC classification number: H01L27/1085

Abstract: A fabricating equipment and method for a semiconductor device is provided. The fabricating equipment comprises a process chamber including an internal space, a substrate support which supports a substrate including a first film and a second film, inside the internal space, a nozzle which is placed on the substrate support and supplies a process gas, a first heater which is placed inside the substrate support and heats the substrate and a second heater which generates one of waves of a first frequency and waves of a second frequency to differentially heat the first film and the second film.

公开(公告)号：US20230212749A1

公开(公告)日：2023-07-06

申请号：US18060861

申请日：2022-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Min PARK ,  Su Hwan Kim ,  Han Jin LIM

IPC: C23C16/455 ,  C23C16/52

CPC classification number: C23C16/45578 ,  C23C16/52 ,  C23C16/45544

Abstract: A device for manufacturing a semiconductor device is provided. The device for manufacturing a semiconductor device includes a tube extending in a first direction, and defining a reaction space therein and configured to accommodate a boat that is configured to receive a plurality of substrates therein, and first and second nozzles each extending in the first direction inside the tube, and being apart from each other on a plane that is perpendicular to the first direction and parallel to upper surfaces of the substrates, wherein the first and second nozzles include a plurality of first injection ports and a plurality of first second injection ports that are configured inject different gases toward a center of the reaction space, respectively, and a plurality of second injection ports are placed in a region between a corresponding pair of adjacent ones of the plurality of first injection ports along the first direction.

公开(公告)号：US20230061185A1

公开(公告)日：2023-03-02

申请号：US17708098

申请日：2022-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Intak JEON ,  Han Jin LIM ,  Hyung Suk JUNG ,  Jae Hyoung CHOI

IPC: H01L27/108

Abstract: A semiconductor device is provided. The semiconductor device comprises a lower electrode, a lower dielectric layer on the lower electrode, an upper electrode on the lower dielectric layer, an upper dielectric layer formed between the lower dielectric layer and the upper electrode, and an interposed electrode film formed between the lower dielectric layer and the upper dielectric layer, wherein the upper dielectric layer includes titanium oxide.

公开(公告)号：US20200266213A1

公开(公告)日：2020-08-20

申请号：US16870082

申请日：2020-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hoon CHOI ,  Sung Gil KIM ,  Seulye KIM ,  Jung Ho KIM ,  Hong Suk KIM ,  Phil Ouk NAM ,  Jae Young AHN ,  Han Jin LIM

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11565

Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.

公开(公告)号：US20190214455A1

公开(公告)日：2019-07-11

申请号：US16012997

申请日：2018-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Yeol KANG ,  Kyo Ho CHO ,  Han Jin LIM ,  Cheol Seong HWANG

IPC: H01L49/02 ,  H01L27/108

Abstract: A semiconductor device including a switching element on a substrate, a pad isolation layer on the switching element, a conductive pad passing through the pad isolation layer and connected to the switching element, an insulating pattern on the pad isolation layer and having a height greater than a horizontal width, a lower electrode on side surfaces of the insulating pattern on side surfaces of the insulating pattern and in contact with the conductive pad, a capacitor dielectric layer on the lower electrode and having a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer an upper electrode on the capacitor dielectric layer may be provided.